| /prebuilts/misc/windows/protobuf2.5/include/google/protobuf/stubs/ |
| atomicops_internals_x86_msvc.h | 67 // acts as a barrier in this implementation
71 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
104 // acts as a barrier in this implementation
108 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
|
| atomicops_internals_x86_gcc.h | 45 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
120 // 64-bit implementations of memory barrier can be simpler, because it
138 NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
148 // acts as a barrier on PIII
155 *ptr = value; // An x86 store acts as a release barrier.
164 Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
234 *ptr = value; // An x86 store acts as a release barrier
257 Atomic64 value = *ptr; // An x86 load acts as a acquire barrier,
|
| /prebuilts/tools/darwin-x86_64/protoc/include/google/protobuf/stubs/ |
| atomicops_internals_x86_msvc.h | 67 // acts as a barrier in this implementation
71 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
104 // acts as a barrier in this implementation
108 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
|
| atomicops_internals_x86_gcc.h | 45 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
120 // 64-bit implementations of memory barrier can be simpler, because it
138 NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
148 // acts as a barrier on PIII
155 *ptr = value; // An x86 store acts as a release barrier.
164 Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
234 *ptr = value; // An x86 store acts as a release barrier
257 Atomic64 value = *ptr; // An x86 load acts as a acquire barrier,
|
| /prebuilts/tools/linux-x86_64/protoc/include/google/protobuf/stubs/ |
| atomicops_internals_x86_msvc.h | 67 // acts as a barrier in this implementation
71 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
104 // acts as a barrier in this implementation
108 *ptr = value; // works w/o barrier for current Intel chips as of June 2005
|
| atomicops_internals_x86_gcc.h | 45 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
120 // 64-bit implementations of memory barrier can be simpler, because it
138 NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
148 // acts as a barrier on PIII
155 *ptr = value; // An x86 store acts as a release barrier.
164 Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
234 *ptr = value; // An x86 store acts as a release barrier
257 Atomic64 value = *ptr; // An x86 load acts as a acquire barrier,
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| barrier.s | 1 @ Test case to validate barrier instruction operands
|
| armv8-a-barrier-arm.d | 1 #name: Valid v8-A barrier (ARM)
3 #source: armv8-a-barrier.s
|
| armv8-a-barrier-thumb.d | 1 #name: Valid v8-A barrier (Thumb)
3 #source: armv8-a-barrier.s
|
| /external/llvm/test/CodeGen/ARM/ |
| swift-atomics.ll | 4 ; Release operations only need the store barrier provided by a "dmb ishst",
40 ; Also, pure acquire operations should definitely not have an ishst barrier.
|
| /external/protobuf/src/google/protobuf/stubs/ |
| atomicops_internals_x86_gcc.h | 45 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
120 // 64-bit implementations of memory barrier can be simpler, because it
138 NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
148 // acts as a barrier on PIII
155 *ptr = value; // An x86 store acts as a release barrier.
164 Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
234 *ptr = value; // An x86 store acts as a release barrier
257 Atomic64 value = *ptr; // An x86 load acts as a acquire barrier,
|
| /external/v8/src/base/ |
| atomicops_internals_arm_gcc.h | 21 // * ARMv5 didn't support SMP, there is no memory barrier instruction at
24 // * Some ARMv6 CPUs support SMP. A full memory barrier can be produced by
28 // barrier (though writing to the co-processor will still work).
36 // perform a memory barrier in the most efficient way. I.e. on single
38 // On multi-core devices, it implements a full memory barrier.
48 // Note: This is a function call, which is also an implicit compiler barrier.
168 // Note that this always perform a full memory barrier, there is no
253 // a memory barrier with no store, which is equivalent to the
|
| atomicops_internals_x86_gcc.h | 18 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
99 // 64-bit implementations of memory barrier can be simpler, because it
117 NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
127 // acts as a barrier on PIII
134 *ptr = value; // An x86 store acts as a release barrier.
147 Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
217 *ptr = value; // An x86 store acts as a release barrier
240 Atomic64 value = *ptr; // An x86 load acts as a acquire barrier,
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| alias.h | 26 unknown, sometimes indicating a memory barrier) and -2 (indicating
46 other memories, creating a barrier across which no memory reference
|
| /prebuilts/misc/darwin-x86_64/protobuf2.5/include/google/protobuf/stubs/ |
| atomicops_internals_x86_gcc.h | 45 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
120 // 64-bit implementations of memory barrier can be simpler, because it
138 NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
148 // acts as a barrier on PIII
155 *ptr = value; // An x86 store acts as a release barrier.
164 Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
234 *ptr = value; // An x86 store acts as a release barrier
257 Atomic64 value = *ptr; // An x86 load acts as a acquire barrier,
|
| /prebuilts/misc/linux-x86_64/protobuf2.5/include/google/protobuf/stubs/ |
| atomicops_internals_x86_gcc.h | 45 bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
120 // 64-bit implementations of memory barrier can be simpler, because it
138 NoBarrier_AtomicExchange(&x, 0); // acts as a barrier on PIII
148 // acts as a barrier on PIII
155 *ptr = value; // An x86 store acts as a release barrier.
164 Atomic32 value = *ptr; // An x86 load acts as a acquire barrier.
234 *ptr = value; // An x86 store acts as a release barrier
257 Atomic64 value = *ptr; // An x86 load acts as a acquire barrier,
|
| /art/test/476-checker-ctor-memory-barrier/src/ |
| Main.java | 90 // Should inline the super constructor and insert a memory barrier.
92 // Should inline the new instance call and insert another memory barrier.
107 // Should inline the super constructor and remove the memory barrier.
130 // Should inline the super constructor and keep just one memory barrier.
133 // Should inline new instance and keep one barrier.
135 // Should inline new instance and keep one barrier.
|
| /external/deqp/framework/delibs/decpp/ |
| deSpinBarrier.hpp | 23 * \brief Cross-thread barrier.
33 * \brief Cross-thread barrier
35 * SpinBarrier provides barrier implementation that uses spin loop for
40 * than number of cores participating in the barrier as it will lead to
60 //! Reset barrier. Not thread-safe, e.g. no other thread can
68 //! Remove thread from barrier (decrements active thread count).
|
| /external/guava/guava-tests/test/com/google/common/util/concurrent/ |
| SerializingExecutorTest.java | 176 final CyclicBarrier barrier = new CyclicBarrier(2); local
191 barrier.await();
199 // the barrier task runs after the error task so we know that the error has been observed by
200 // SerializingExecutor by the time the barrier is satified
201 barrier.await(10, TimeUnit.SECONDS);
204 barrier.await(10, TimeUnit.SECONDS);
|
| /external/autotest/server/ |
| base_utils.py | 13 from autotest_lib.client.common_lib import barrier, utils
335 sc_bar is a server barrier and s_bar, c_bar are the normal barriers
354 @param port_base: Port number that is used to derive the actual barrier
370 # The barrier code snippet is prepended into the conrol file
385 # Do the setup and wait at the server barrier
393 'b0 = job.barrier("%s", "sc_bar", %d, port=%d)'
400 # Wait at the server barrier to wait for instance=0
402 b0 = barrier.barrier("PARALLEL_MASTER", "sc_bar", sc_bar_timeout,
407 b1 = barrier.barrier(jobid, "s_bar", s_bar_timeout
[all...] |
| /external/deqp/android/cts/master/ |
| gles31-multisample.txt | 79 dEQP-GLES31.functional.blend_equation_advanced.barrier.multiply
80 dEQP-GLES31.functional.blend_equation_advanced.barrier.screen
81 dEQP-GLES31.functional.blend_equation_advanced.barrier.overlay
82 dEQP-GLES31.functional.blend_equation_advanced.barrier.darken
83 dEQP-GLES31.functional.blend_equation_advanced.barrier.lighten
84 dEQP-GLES31.functional.blend_equation_advanced.barrier.colordodge
85 dEQP-GLES31.functional.blend_equation_advanced.barrier.colorburn
86 dEQP-GLES31.functional.blend_equation_advanced.barrier.hardlight
87 dEQP-GLES31.functional.blend_equation_advanced.barrier.softlight
88 dEQP-GLES31.functional.blend_equation_advanced.barrier.differenc
[all...] |
| /external/deqp/android/cts/mnc/ |
| gles31-multisample.txt | 79 dEQP-GLES31.functional.blend_equation_advanced.barrier.multiply
80 dEQP-GLES31.functional.blend_equation_advanced.barrier.screen
81 dEQP-GLES31.functional.blend_equation_advanced.barrier.overlay
82 dEQP-GLES31.functional.blend_equation_advanced.barrier.darken
83 dEQP-GLES31.functional.blend_equation_advanced.barrier.lighten
84 dEQP-GLES31.functional.blend_equation_advanced.barrier.colordodge
85 dEQP-GLES31.functional.blend_equation_advanced.barrier.colorburn
86 dEQP-GLES31.functional.blend_equation_advanced.barrier.hardlight
87 dEQP-GLES31.functional.blend_equation_advanced.barrier.softlight
88 dEQP-GLES31.functional.blend_equation_advanced.barrier.differenc
[all...] |
| /external/chromium-trace/catapult/third_party/pipeline/pipeline/ |
| models.py | 171 """Represents a barrier.
173 Key name is the purpose of the barrier (START or FINALIZE). Parent entity
174 is the _PipelineRecord the barrier should trigger when all of its
179 target: The pipeline to run when the barrier fires.
180 blocking_slots: The slots that must be filled before this barrier fires.
181 trigger_time: When this barrier fired.
182 status: The current status of the barrier.
185 # Barrier statuses
189 # Barrier trigger reasons (used as key names)
219 This entity is used to make it so barrier fan-out is fully consisten
[all...] |
| /external/opencv3/modules/calib3d/ |
| opencl_kernels_calib3d.cpp | 26 "barrier(CLK_LOCAL_MEM_FENCE);\n"
32 "barrier(CLK_LOCAL_MEM_FENCE);\n"
112 "barrier(CLK_LOCAL_MEM_FENCE);\n"
164 "barrier(CLK_LOCAL_MEM_FENCE);\n"
167 "barrier(CLK_LOCAL_MEM_FENCE);\n"
171 "barrier(CLK_LOCAL_MEM_FENCE);\n"
180 "barrier(CLK_LOCAL_MEM_FENCE);\n"
193 "barrier(CLK_LOCAL_MEM_FENCE);\n"
196 "barrier(CLK_LOCAL_MEM_FENCE);\n"
200 "barrier(CLK_LOCAL_MEM_FENCE);\n
[all...] |
| /external/opencv3/modules/calib3d/src/opencl/ |
| stereobm.cl | 64 barrier(CLK_LOCAL_MEM_FENCE);
72 barrier(CLK_LOCAL_MEM_FENCE);
163 barrier(CLK_LOCAL_MEM_FENCE);
220 barrier(CLK_LOCAL_MEM_FENCE);
224 barrier(CLK_LOCAL_MEM_FENCE);
229 barrier(CLK_LOCAL_MEM_FENCE);
241 barrier(CLK_LOCAL_MEM_FENCE);
255 barrier(CLK_LOCAL_MEM_FENCE);
259 barrier(CLK_LOCAL_MEM_FENCE);
265 barrier(CLK_LOCAL_MEM_FENCE)
[all...] |
