| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
123 emitMask(BaseReg, LoadStoreStackMaskReg, STI);
|
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 245 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
250 bool HasBaseReg = BaseReg.getReg() != 0;
252 BaseReg.getReg() == X86::RIP)
310 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
325 if (BaseReg.getReg()) {
343 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
|
| X86SelectionDAGInfo.cpp | 40 unsigned BaseReg = TRI->getBaseRegister();
42 if (BaseReg == R)
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| m68k-dis.c | 517 /* Print an indexed argument. The base register is BASEREG (-1 for pc).
523 print_indexed (int basereg,
551 if (basereg == -1)
553 print_base (basereg, base_disp, info);
562 if (basereg == -1)
563 basereg = -3;
565 basereg = -2;
578 if (basereg == -1)
584 print_base (basereg, base_disp, info);
602 print_base (basereg, base_disp, info)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | [all...] |
| Thumb2SizeReduction.cpp | 128 // ARM::t2STMIA (with no basereg writeback) has no Thumb1 equivalent.
421 unsigned BaseReg = MI->getOperand(0).getReg();
422 assert(isARMLowRegister(BaseReg));
428 if (MI->getOperand(i).getReg() == BaseReg) {
450 unsigned BaseReg = MI->getOperand(1).getReg();
451 if (BaseReg != ARM::SP)
463 unsigned BaseReg = MI->getOperand(1).getReg();
464 if (BaseReg == ARM::SP &&
469 } else if (!isARMLowRegister(BaseReg) ||
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 165 unsigned BaseReg = Base.getReg();
181 .addReg(BaseReg).addImm(Amt)
188 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
193 .addReg(BaseReg).addReg(OffReg)
204 .addReg(BaseReg).addImm(Amt)
209 .addReg(BaseReg).addReg(OffReg)
231 .addReg(BaseReg).addImm(0).addImm(Pred);
235 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
[all...] |
| /external/llvm/lib/CodeGen/ |
| ImplicitNullChecks.cpp | 327 unsigned BaseReg, Offset;
328 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI))
329 if (MI->mayLoad() && !MI->isPredicable() && BaseReg == PointerReg &&
|
| CodeGenPrepare.cpp | [all...] |
| TargetInstrInfo.cpp | [all...] |
| MachineScheduler.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 93 bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
97 bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| LoopStrengthReduce.cpp | 460 for (const SCEV *BaseReg : BaseRegs)
461 if (RegUses.isRegUsedByUsesOtherThan(BaseReg, LUIdx))
476 for (const SCEV *BaseReg : BaseRegs) {
478 OS << "reg(" << *BaseReg << ')';
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/rsc.io/x86/x86asm/ |
| decode.go | 1038 base := baseReg[x]
1049 inst.Args[narg] = baseReg[x] + Reg(regop&7)
1074 base := baseReg[x]
1085 base := baseReg[x]
1106 base := baseReg[x]
1128 inst.Args[narg] = baseReg[x] + Reg(rm&7)
1136 inst.Args[narg] = baseReg[x] + Reg(rm)
[all...] |
| /prebuilts/go/linux-x86/src/cmd/internal/rsc.io/x86/x86asm/ |
| decode.go | 1038 base := baseReg[x]
1049 inst.Args[narg] = baseReg[x] + Reg(regop&7)
1074 base := baseReg[x]
1085 base := baseReg[x]
1106 base := baseReg[x]
1128 inst.Args[narg] = baseReg[x] + Reg(rm&7)
1136 inst.Args[narg] = baseReg[x] + Reg(rm)
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 680 unsigned BaseReg = 0;
682 if (ParseRegister(BaseReg, S, E)) {
692 Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
708 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
709 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | [all...] |
| TargetInstrInfo.h | 402 /// \p [out] BaseReg and \p [out] InsertedReg contain
405 /// - BaseReg: vreg0:sub0
418 RegSubRegPair &BaseReg,
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| Store.cpp | 274 const MemRegion *BaseReg =
278 return loc::MemRegionVal(BaseReg);
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 40 unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
41 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SReg_128RegClass);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonStoreWidening.cpp | 243 unsigned BaseReg = getBaseAddressRegister(BaseStore);
264 if (BR == BaseReg) {
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-i370.c | 2053 int basereg = -1; local
[all...] |
| /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| MemRegion.h | [all...] |
