| /external/llvm/test/CodeGen/Mips/ |
| fpbr.ll | 14 ; FCC: bc1f $BB0_2 48 ; FCC: bc1f $BB1_2 106 ; FCC: bc1f $BB3_2 136 ; FCC: bc1f $BB4_2
|
| /external/llvm/test/MC/Mips/mips1/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/valgrind/none/tests/mips64/ |
| macro_fpu.h | 320 "bc1f end"instruction"s"#RDval "\n\t" \ 330 printf("%s, bc1f out=%f, fs=%f, ft=%f\n", \ 343 "bc1f end"instruction"d"#RDval "\n\t" \ 353 printf("%s, bc1f out=%f, fs=%f, ft=%f\n", \
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| micromips@mips4-fp.d | 11 [0-9a-f]+ <[^>]*> 4380 fffe bc1f 0+0000 <text_label> 14 [0-9a-f]+ <[^>]*> 4384 fffe bc1f \$fcc1,0+0006 <text_label\+0x6>
|
| mips4-fp.l | 2 .*:4: Error: opcode not supported on this processor: .* \(.*\) `bc1f text_label' 3 .*:5: Error: opcode not supported on this processor: .* \(.*\) `bc1f \$fcc1,text_label'
|
| micromips-branch-relax.s | 95 bc1f test3
|
| /external/llvm/test/MC/Mips/ |
| mips-jump-instructions.s | 13 # CHECK32: bc1f 1332 # encoding: [0x4d,0x01,0x00,0x45] 38 # CHECK64: bc1f 1332 # encoding: [0x4d,0x01,0x00,0x45] 65 bc1f 1332
|
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 317 case Mips::BC1F: 318 // bc1f $fcc0, $L1 => bc1f $L1 319 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
|
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| invalid-mips32.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] 21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] 21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] 21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] 21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] 21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] 21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] 21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] 21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] 21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] 21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/lib/Target/Mips/ |
| MicroMipsInstrFPU.td | 40 def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] 20 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| select.ll | 387 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] 419 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] 483 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] 586 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] 618 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] 682 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
|