| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| valid-mips32r2.txt | 179 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
180 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
185 0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| valid-mips32r3.txt | 176 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
177 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
182 0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| valid-mips32r5.txt | 176 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
177 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
182 0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64.txt | 217 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
218 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
223 0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
|
| valid-mips64-el.txt | 13 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
14 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips1/ |
| valid-mips1-el.txt | 15 0x01 0x00 0x00 0x45 # CHECK: bc1f 8
|
| valid-mips1.txt | 73 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
|
| /external/llvm/test/MC/Disassembler/Mips/mips2/ |
| valid-mips2-el.txt | 16 0x01 0x00 0x00 0x45 # CHECK: bc1f 8
|
| valid-mips2.txt | 110 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips4.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/valgrind/coregrind/m_gdbserver/ |
| valgrind-low-mips32.c | 181 && (rs == 8 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
|
| valgrind-low-mips64.c | 182 && (rs == 8 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| relax-swap1-mips1.d | 167 0+020c <[^>]*> bc1f 00000224 <foo\+0x224>
|
| relax-swap1-mips2.d | 148 0+01c0 <[^>]*> bc1f 000001d4 <foo\+0x1d4>
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4.txt | 149 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
153 0x45 0x04 0x00 0x00 # CHECK: bc1f $fcc1, 4
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2-el.txt | 17 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
18 0x4c 0x01 0x1c 0x45 # CHECK: bc1f $fcc7, 1332
|
| valid-mips64r2.txt | 237 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
238 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
243 0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| valid-mips64r3.txt | 235 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
236 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
241 0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| valid-mips64r5.txt | 234 0x45 0x00 0x00 0x01 # CHECK: bc1f 8
235 0x45 0x00 0x01 0x4c # CHECK: bc1f 1332
240 0x45 0x1c 0x01 0x4c # CHECK: bc1f $fcc7, 1332
|
| /external/pcre/dist/sljit/ |
| sljitNativeMIPS_common.c | 106 #define BC1F (HI(17) | (8 << 21))
[all...] |
| /external/v8/src/mips/ |
| assembler-mips.h | [all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.h | [all...] |
