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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
arm6.s 4 mrs r8, cpsr
7 msr cpsr, r1
12 mrs r8, CPSR
15 msr CPSR, r1
mrs-msr-thumb-v6t2.s 6 mrs r5, cpsr
mrs-msr-arm-v6.s 6 mrs r5, cpsr
mrs-msr-arm-v7-a.s 6 mrs r5, cpsr
mrs-msr-thumb-v7-m-bad.s 5 mrs r4, cpsr
mrs-msr-arm-v6.d 8 0+00 <[^>]*> e10f4000 mrs r4, CPSR
9 0+04 <[^>]*> e10f5000 mrs r5, CPSR
mrs-msr-arm-v7-a.d 8 0+00 <[^>]*> e10f4000 mrs r4, CPSR
9 0+04 <[^>]*> e10f5000 mrs r5, CPSR
mrs-msr-thumb-v6t2.d 10 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
11 0+04 <[^>]*> f3ef 8500 mrs r5, CPSR
mrs-msr-arm-v7-a-bad.l 2 [^:]*:5: Error: 'APSR', 'CPSR' or 'SPSR' expected -- `mrs r4,apsr_nzcvq'
arm6.d 8 0+00 <[^>]+> e10f8000 ? mrs r8, CPSR
14 0+18 <[^>]+> e10f8000 ? mrs r8, CPSR
  /external/valgrind/none/tests/arm/
v6intThumb.stdout.exp 2 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
3 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
4 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
5 cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
6 cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000
7 cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V
8 cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C
9 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC
10 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C
11 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N
    [all...]
v6intARM.stdout.exp 2 mov r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
3 cpy r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
4 mov r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x00000000
5 mov r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000
6 movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
7 movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000 Z
8 movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 0, cpsr 0x80000000 N
9 movs r0, #0 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000 Z
10 movs r0, #1 :: rd 0x00000001 rm 0x00000000, carryin 0, cpsr 0x00000000
11 movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000 C
    [all...]
v6media.stdout.exp 2 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
3 mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[3:0]=0000
4 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
5 mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
6 mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
7 mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000 ge[3:0]=0000
9 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
10 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
11 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=0000
12 mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x00000000 ge[3:0]=000
    [all...]
  /external/llvm/test/CodeGen/MIR/ARM/
bundled-instructions.mir 32 ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
33 ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
35 ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate
40 t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
41 BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
43 %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate
62 ; CHECK-NEXT: t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
63 ; CHECK-NEXT: BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
65 ; CHECK-NEXT: %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit internal killed %itstate
70 t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
    [all...]
expected-closing-brace.mir 37 t2CMNri %r0, 78, 14, _, implicit-def %cpsr
39 BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
41 %r1 = t2MOVi 1, 12, killed %cpsr, _, implicit killed %itstate
42 t2CMNri %r0, 77, 14, _, implicit-def %cpsr
43 t2Bcc %bb.1.foo, 11, killed %cpsr
nested-instruction-bundle-error.mir 20 t2CMNri killed %r0, 78, 14, _, implicit-def %cpsr
21 BUNDLE implicit-def dead %itstate, implicit-def %r1, implicit killed %cpsr {
23 %r1 = t2MOVi 1, 12, killed %cpsr, _
  /external/compiler-rt/test/builtins/Unit/arm/
aeabi_cdcmple_test.c 50 union cpsr cpsr = { .value = cpsr_value }; local
51 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
53 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c);
57 cpsr.value = r_cpsr_value;
58 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
60 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c)
    [all...]
aeabi_cfcmple_test.c 50 union cpsr cpsr = { .value = cpsr_value }; local
51 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
53 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c);
57 cpsr.value = r_cpsr_value;
58 if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) {
60 a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c)
    [all...]
aeabi_cdcmpeq_test.c 27 union cpsr cpsr = { .value = cpsr_value }; local
28 if (expected != cpsr.flags.z) {
30 a, b, cpsr.flags.z, expected);
aeabi_cfcmpeq_test.c 27 union cpsr cpsr = { .value = cpsr_value }; local
28 if (expected != cpsr.flags.z) {
30 a, b, cpsr.flags.z, expected);
  /external/valgrind/coregrind/m_gdbserver/
arm-core.xml 27 <!-- The CPSR is register 25, rather than register 16, because
29 and the CPSR in the "g" packet. -->
30 <reg name="cpsr" bitsize="32" regnum="25"/>
arm-core-valgrind-s1.xml 27 <!-- The CPSR is register 25, rather than register 16, because
29 and the CPSR in the "g" packet. -->
arm-core-valgrind-s2.xml 27 <!-- The CPSR is register 25, rather than register 16, because
29 and the CPSR in the "g" packet. -->
  /external/llvm/test/CodeGen/AArch64/
arm64-2011-04-21-CPSRBug.ll 3 ; CPSR is not allocatable so fast allocatable wouldn't mark them killed.
  /external/llvm/test/CodeGen/ARM/
copy-cpsr.ll 5 ; In the ARM backend, most compares are glued to their uses so CPSR can't
8 ; copying CPSR.
14 ; CPSR is used twice).
15 ; + We want both chains to write CPSR post-split (so that the copy can't be

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