| /external/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.cpp | 158 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
159 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
|
| AggressiveAntiDepBreaker.cpp | 439 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
440 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
[all...] |
| EarlyIfConversion.cpp | 185 // Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| sparc-dis.c | 76 /* psr, wim, tbr, fpsr, cpsr are v8 only. */
77 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 566 // implicitly set CPSR. Since it's not represented in the encoding, the
567 // auto-generated decoder won't inject the CPSR operand. We need to fix
577 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
582 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
646 MI.insert(I, MCOperand::createReg(ARM::CPSR));
656 MI.insert(I, MCOperand::createReg(ARM::CPSR));
682 I->setReg(ARM::CPSR);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrFormats.td | 177 // Same as cc_out except it defaults to setting CPSR.
178 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
446 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
[all...] |
| ARMISelDAGToDAG.cpp | 139 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
[all...] |
| ARMExpandPseudoInsts.cpp | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 928 O << "CPSR";
1018 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
1019 "Expect ARM CPSR register!");
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 267 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
269 return MI.getOperand(Op).getReg() == ARM::CPSR;
691 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
[all...] |
| /external/v8/tools/ |
| grokdump.py | 344 ("cpsr", ctypes.c_uint32),
396 ("cpsr", ctypes.c_uint32),
[all...] |
| /development/scripts/ |
| stack_core.py | 58 "arm": "r0|r1|r2|r3|r4|r5|r6|r7|r8|r9|sl|fp|ip|sp|lr|pc|cpsr",
|
| /external/google-breakpad/src/processor/ |
| synth_minidump_unittest_data.h | 268 // cpsr
|
| /system/core/libpixelflinger/codeflinger/ |
| disassem.c | 458 di->di_printf("cpsr");
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| msr-imm-bad.l | 6 [^:]*:15: Error: Thumb encoding does not support an immediate here -- `msr CPSR,#0xc0000004'
|
| msr-reg-bad.l | 5 [^:]*:14: Error: selected processor does not support requested special purpose register -- `msr CPSR,r9'
|
| thumb2_bad_reg.l | 165 [^:]*:[0-9]+: Error: r13 not allowed here -- `mrs r13,cpsr'
166 [^:]*:[0-9]+: Error: r15 not allowed here -- `mrs r15,cpsr'
167 [^:]*:[0-9]+: Error: r13 not allowed here -- `msr cpsr,r13'
168 [^:]*:[0-9]+: Error: r15 not allowed here -- `msr cpsr,r15'
[all...] |
| thumb32.s | 469 mrs r0, CPSR
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-arm.c | 479 /* The bit that distinguishes CPSR and SPSR. */
[all...] |
| /external/valgrind/VEX/priv/ |
| host_arm_defs.h | 801 /* 64-bit FP compare and move results to CPSR (FCMPD;FMSTAT) */
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/ |
| armCOMM_s.h | 872 MRS r4, cpsr ;// preserve flags variable
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_s.h | 875 MRS r4, cpsr ;// preserve flags variable
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/sysroot/usr/include/alsa/ |
| iatomic.h | 906 "mrs %0, cpsr @ local_irq_save\n" \
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/alsa/ |
| iatomic.h | 906 "mrs %0, cpsr @ local_irq_save\n" \
|
