| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_reg.h | 454 /* subsequent dwords up to length (max 16) are ARGB8888 color values */
492 /* Each instruction is 3 dwords long, though most don't require all
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_blit.c | 307 unsigned dwords = local
313 if (dwords > (RADEON_MAX_CMDBUF_DWORDS - r300->cs->cdw)) {
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| radeonsi_shader.c | 114 * elements to offset, not the number of bytes or dwords. An element is the
144 * type. For example, if the value being loaded is two dwords wide, then the sgpr
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| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| i915_reg.h | 333 /* subsequent dwords up to length (max 16) are ARGB8888 color values */
364 /* Each instruction is 3 dwords long, though most don't require all
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/x86/ |
| vp9_postproc_sse2.asm | 524 punpcklwd xmm1, xmm0 ; expanding to dwords
525 punpcklwd xmm2, xmm0 ; expanding to dwords
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| /external/mesa3d/src/gallium/drivers/r600/ |
| r600_hw_context.c | 648 /* The number of dwords we already used in the CS so far. */
652 /* The number of dwords all the dirty states would take. */
678 /* Save 16 dwords for the fence mechanism. */
[all...] |
| /hardware/intel/img/psb_video/src/ |
| psb_cmdbuf.c | 336 reloc->where = addr_in_cmdbuf - (uint32_t *) cmdbuf->cmd_base; /* Location in DWORDs */
340 reloc->where = addr_in_cmdbuf - (uint32_t *) cmdbuf->MTX_msg; /* Location in DWORDs */
789 MEMIO_WRITE_FIELD(msg, FW_DEVA_DECODE_BUFFER_SIZE, cmdbuffer_size / 4); // In dwords
[all...] |
| pnw_cmdbuf.c | 275 reloc->where = addr_in_dst_buffer - start_of_dst_buffer; /* Offset in DWORDs */
|
| tng_cmdbuf.c | 338 reloc->where = addr_in_dst_buffer - start_of_dst_buffer; /* Offset in DWORDs */
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstrInfo.td | 181 // src1: dst - rat offset (aka pointer) in dwords
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| arguments-float.ll | 20 @dwords = global [11 x i64] zeroinitializer
|
| arguments-hard-float.ll | 20 @dwords = global [11 x i64] zeroinitializer
|
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_debug.c | 75 debug_printf("%s (%d dwords%s)\n", name, size/4,
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelDAGToDAG.cpp | 339 // so we need to convert it to dwords.
|
| /external/mesa3d/src/gallium/drivers/svga/svgadump/ |
| svga_shader_dump.c | 558 unsigned dwords,
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vs.c | 80 /* There are 8 dwords in VUE header pre-Ironlake:
|
| brw_context.h | 64 * spawned. The registers are individually 8 dwords wide and suitable
437 GLuint nr_pull_params; /**< number of dwords referenced by pull_param[] */
[all...] |
| brw_eu.h | 92 GLuint pad1:10; /* two dwords total */
|
| gen6_blorp.cpp | 228 * Fetch dwords 0 - 7 from each VUE. See the comments above where
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/intel/ |
| intel_batchbuffer.c | 239 /* Round batchbuffer usage to 2 DWORDs. */
|
| /hardware/intel/img/psb_video/src/mrst/ |
| lnc_cmdbuf.c | 266 reloc->where = addr_in_dst_buffer - start_of_dst_buffer; /* Offset in DWORDs */
|
| /external/libdrm/amdgpu/ |
| amdgpu.h | 284 * - The size is in units of dwords (4 bytes).
1061 * \param dword_offset - \c [in] Register offset in dwords
[all...] |
| /external/boringssl/src/crypto/sha/asm/ |
| sha1-x86_64.pl | 554 &psrldq (@Tx[0],4); # "X[-3]", 3 dwords
1004 &vpsrldq(@Tx[0],@X[-1&7],4); # "X[-3]", 3 dwords
[all...] |
| /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/compile/internal/arm64/ |
| ggen.go | 422 q := uint64(w / 8) // dwords
|
| /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/compile/internal/ppc64/ |
| ggen.go | 414 q := uint64(w / 8) // dwords
|
