| /external/llvm/tools/llvm-mcmarkup/ |
| llvm-mcmarkup.cpp | 102 // Color registers as red and immediates as cyan. Those don't have nested
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| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_context.h | 129 * Else, the bitmask indicates which components are occupied by immediates.
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| i915_fpc.h | 58 float immediates[I915_MAX_CONSTANT][4]; member in struct:i915_fp_compile
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| i915_fpc_translate.c | [all...] |
| /external/v8/src/arm64/ |
| instructions-arm64.cc | 89 // Logical immediates can't encode zero, so a return value of zero is used to
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| /external/v8/src/compiler/ |
| instruction.h | 1268 Immediates& immediates() { return immediates_; } function in class:v8::internal::compiler::final
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86Operand.h | 377 // Add as immediates when possible.
439 // Add as immediates when possible.
458 // Add as immediates when possible.
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_aos.c | 180 LLVMValueRef res = bld->immediates[reg->Register.Index];
1049 /* simply copy the immediate values into the next immediates[] slot */
1062 bld.immediates[num_immediates] =
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| lp_bld_tgsi_soa.c | 643 LLVMValueRef res = bld->immediates[reg->Register.Index][swizzle];
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| radeon_setup_tgsi_llvm.c | 128 return LLVMConstBitCast(bld->immediates[reg->Register.Index][swizzle], ctype);
666 bld->immediates[off->Index][off->SwizzleX],
669 bld->immediates[off->Index][off->SwizzleY],
672 bld->immediates[off->Index][off->SwizzleZ],
944 ctx->soa.immediates[ctx->soa.num_immediates][i] =
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.cpp | [all...] |
| X86Disassembler.cpp | 321 // By default sign-extend all X86 immediates based on their encoding.
343 // Check for immediates that printSSECC can't handle.
377 // Check for immediates that printAVXCC can't handle.
[all...] |
| /external/v8/test/unittests/compiler/arm64/ |
| instruction-selector-arm64-unittest.cc | 78 // ARM64 logical immediates: contiguous set bits, rotated about a power of two
80 // subset of the 32-bit immediates.
101 // Random subset of 64-bit logical immediates.
153 // ARM64 Add/Sub immediates: 12-bit immediate optionally shifted by 12.
356 // TODO(all): Add support for testing 64-bit immediates.
752 // that immediates outside this range are handled properly (modulo-32).
776 // that immediates outside this range are handled properly (modulo-64).
2119 const int32_t immediates[20]; member in struct:v8::internal::compiler::__anon25314::MemoryAccess
[all...] |
| /external/mesa3d/src/mesa/state_tracker/ |
| st_glsl_to_tgsi.cpp | 358 exec_list immediates; member in class:glsl_to_tgsi_visitor
545 assert(!"immediates should not have indirect addressing");
567 assert(!"immediates should not have indirect addressing");
881 foreach_iter(exec_list_iterator, iter, this->immediates) {
894 this->immediates.push_tail(entry);
3894 struct ureg_src *immediates; member in struct:st_translate
[all...] |
| /external/v8/test/unittests/compiler/mips64/ |
| instruction-selector-mips64-unittest.cc | 362 // that immediates outside this range are handled properly (modulo-32).
402 // that immediates outside this range are handled properly (modulo-64).
611 // that immediates outside this range are handled properly (modulo-32).
650 // that immediates outside this range are handled properly (modulo-64).
1022 const int32_t immediates[40]; member in struct:v8::internal::compiler::__anon25343::MemoryAccessImm
1037 const int32_t immediates[5]; member in struct:v8::internal::compiler::__anon25343::MemoryAccessImm1
[all...] |
| /external/libgdx/extensions/gdx-freetype/jni/freetype-2.6.2/src/type42/ |
| t42parse.c | 394 /* we only read immediates. */
472 /* immediates-only mode we would get an infinite loop if */
[all...] |
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 205 // immediates anyway.
246 // immediates). Note that this causes us to reject variable sized shifts
601 // If any of the operands were immediates with predicates on them, strip
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| /external/llvm/include/llvm-c/ |
| Disassembler.h | 218 /* The option to print immediates as hex. */
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 82 /// This refers to scaling a dynamic index as opposed to scaled immediates.
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| /external/llvm/lib/Target/AMDGPU/ |
| SIShrinkInstructions.cpp | 220 // Try to use S_MOVK_I32, which will save 4 bytes for small immediates.
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| /external/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.td | 133 // 8-bit register class for instructions which take immediates.
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| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 93 /// rotate amt is zero. We also have to munge the immediates a bit.
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| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 129 // Emit nonnegaive immediates with sethi + or.
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.td | 301 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF,
308 // Other 16-bit immediates.
314 // 32-bit immediates.
678 // ...likewise for 32-bit immediates. For GR32s this is a general
710 // Addition of signed 16-bit immediates.
715 // Addition of signed 32-bit immediates.
[all...] |
| /external/valgrind/docs/internals/ |
| t-chaining-notes.txt | 162 targets, since no immediates need to be synthesised, eg:
|
