| /external/clang/lib/Basic/ |
| Targets.cpp | [all...] |
| /external/llvm/docs/ |
| Atomics.rst | 442 which take some sort of exclusive lock on a cache line (``LDREX`` and ``STREX``
|
| /external/llvm/lib/CodeGen/ |
| AtomicExpandPass.cpp | 317 // atomic swap, that can be implemented for example as a ldrex/strex on ARM
|
| /external/opencv3/3rdparty/libwebp/cpu-features/ |
| cpu-features.c | 639 /* The LDREX / STREX instructions are available from ARMv6 */
|
| /external/valgrind/VEX/priv/ |
| host_arm64_defs.h | 665 } LdrEX;
[all...] |
| host_arm_defs.c | [all...] |
| host_arm64_defs.c | [all...] |
| /art/runtime/arch/arm/ |
| quick_entrypoints_arm.S | 540 ldrex r1, [r0, #MIRROR_OBJECT_LOCK_WORD_OFFSET]
597 ldrex r1, [r0, #MIRROR_OBJECT_LOCK_WORD_OFFSET] @ Need to use atomic instructions for read barrier
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMScheduleSwift.td | 342 "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)",
[all...] |
| /external/skia/platform_tools/android/third_party/cpufeatures/ |
| cpu-features.c | 757 /* The LDREX / STREX instructions are available from ARMv6 */
[all...] |
| /prebuilts/go/darwin-x86/src/runtime/ |
| asm_arm.s | 716 LDREX (R1), R0
|
| /prebuilts/go/linux-x86/src/runtime/ |
| asm_arm.s | 716 LDREX (R1), R0
|
| /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/internal/obj/arm/ |
| asm5.go | [all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/arm/ |
| asm5.go | [all...] |
| /prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/internal/obj/arm/ |
| asm5.go | [all...] |
| /prebuilts/go/linux-x86/src/cmd/internal/obj/arm/ |
| asm5.go | [all...] |
| /art/compiler/utils/arm/ |
| assembler_thumb2.cc | 2725 void Thumb2Assembler::ldrex(Register rt, Register rn, uint16_t imm, Condition cond) { function in class:art::arm::Thumb2Assembler
2740 void Thumb2Assembler::ldrex(Register rt, Register rn, Condition cond) { function in class:art::arm::Thumb2Assembler
[all...] |
| assembler_arm32.cc | 830 void Arm32Assembler::ldrex(Register rt, Register rn, Condition cond) { function in class:art::arm::Arm32Assembler
[all...] |
| /ndk/sources/android/cpufeatures/ |
| cpu-features.c | 767 /* The LDREX / STREX instructions are available from ARMv6 */
[all...] |
| /external/clang/docs/ |
| LanguageExtensions.rst | [all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/ |
| ChangeLog-2005 | 141 * gas/arm/archv6t2-bad.s: Add tests of badly composed ldrex and
144 * gas/arm/r15-bad.l: Adjust error messages for r15 usage in ldrex
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb2-instructions.s | [all...] |
| /art/compiler/optimizing/ |
| intrinsics_arm.cc | [all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| thumb2.txt | 707 # LDREX/LDREXB/LDREXH/LDREXD
709 # CHECK: ldrex r1, [r4]
710 # CHECK: ldrex r8, [r4]
711 # CHECK: ldrex r2, [sp, #128]
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| thumb32.d | 554 0[0-9a-f]+ <[^>]+> e854 1f00 ldrex r1, \[r4\]
561 0[0-9a-f]+ <[^>]+> e854 1f81 ldrex r1, \[r4, #516\].*
[all...] |
