| /external/llvm/test/CodeGen/AArch64/ |
| arm64-fast-isel-conversion.ll | 112 ; CHECK: ldrsw x3, [sp, #8]
|
| ldst-unsignedimm.ll | 141 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit]
|
| arm64-indexed-memory.ll | 332 ; CHECK: ldrsw x[[REG:[0-9]+]], [x0, #4]!
|
| ldst-regoffset.ll | 124 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{[xw][0-9]+}}, sxtw]
|
| /external/v8/src/full-codegen/arm64/ |
| full-codegen-arm64.cc | [all...] |
| /external/llvm/test/MC/AArch64/ |
| basic-a64-instructions.s | [all...] |
| basic-a64-diagnostics.s | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | 648 ### LDRSW ###
652 void ldrsw(const Register& rt, RawLiteral* literal)
655 ### LDRSW ###
659 void ldrsw(const Register& rt, int imm19)
662 ### LDRSW ###
666 void ldrsw(const Register& rt, const MemOperand& src,
[all...] |
| /external/v8/src/arm64/ |
| code-stubs-arm64.cc | [all...] |
| macro-assembler-arm64.cc | [all...] |
| disasm-arm64.cc | 753 V(LDRSW_x, "ldrsw", "'Xt") \
[all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | [all...] |
| test-assembler-a64.cc | [all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.h | 49 V(Ldrsw, Register&, rt, LDRSW_x)
[all...] |
| assembler-a64.h | [all...] |
| assembler-a64.cc | [all...] |
| disasm-a64.cc | 791 V(LDRSW_x, "ldrsw", "'Xt") \
916 mnemonic = "ldrsw";
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-tbl.h | 91 /* e.g. LDRSW <Xt>, <label>. */
1034 /* e.g. LDRSW <Xt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
[all...] |
| aarch64-asm.c | 533 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */
565 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]. */
[all...] |
| aarch64-dis-2.c | 600 ldrsw. */
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| basic-a64-instructions.txt | [all...] |
| /external/v8/src/ic/arm64/ |
| handler-compiler-arm64.cc | 423 __ Ldrsw(scratch, FieldMemOperand(map_reg, Map::kBitField3Offset));
|
| /external/valgrind/none/tests/arm64/ |
| memory.stdout.exp | 32 ldrsw x21, [x22, #24] :: rd ffffffff8b8a8988 rn (hidden), cin 0, nzcv 00000000
38 ldrsw x21, [x22, #-24]! :: rd ffffffffdbdad9d8 rn (hidden), cin 0, nzcv 00000000
43 ldrsw x21, [x22], #-24 :: rd fffffffff3f2f1f0 rn (hidden), cin 0, nzcv 00000000
49 ldrsw x21, [x22, #-24] :: rd ffffffffdbdad9d8 rn (hidden), cin 0, nzcv 00000000
57 ldrsw x21, [x22,x23] :: rd fffffffff8f7f6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
58 ldrsw x21, [x22,x23, lsl #2] :: rd ffffffff87868584 rm (hidden), rn (hidden), cin 0, nzcv 00000000
59 ldrsw x21, [x22,w23,uxtw #0] :: rd fffffffff8f7f6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000
60 ldrsw x21, [x22,w23,uxtw #2] :: rd ffffffff87868584 rm (hidden), rn (hidden), cin 0, nzcv 00000000
61 ldrsw x21, [x22,w23,sxtw #0] :: rd ffffffffeeedeceb rm (hidden), rn (hidden), cin 0, nzcv 00000000
62 ldrsw x21, [x22,w23,sxtw #2] :: rd ffffffffdfdedddc rm (hidden), rn (hidden), cin 0, nzcv 00000000
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | [all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | [all...] |
