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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
nan-2008-4.d 1 #name: MIPS 2008 NaN setting 4
6 .*:.*file format.*mips.*
odd-float.d 2 #name: MIPS odd float
5 .*: +file format .*mips.*
attr-gnu-4-1.d 4 #name: MIPS gnu_attribute 4,1 (double precision)
10 MIPS ABI Flags Version: 0
12 ISA: MIPS.*
attr-gnu-4-2.d 5 #name: MIPS gnu_attribute 4,2 (single precision)
11 MIPS ABI Flags Version: 0
13 ISA: MIPS.*
attr-gnu-4-3.d 5 #name: MIPS gnu_attribute 4,3 (-msoft-float)
11 MIPS ABI Flags Version: 0
13 ISA: MIPS.*
attr-gnu-4-5.d 5 #name: MIPS gnu_attribute 4,5 (-mfpxx)
11 MIPS ABI Flags Version: 0
13 ISA: MIPS.*
attr-gnu-4-6.d 5 #name: MIPS gnu_attribute 4,6 (-mfp64)
11 MIPS ABI Flags Version: 0
13 ISA: MIPS.*
attr-gnu-4-7.d 5 #name: MIPS gnu_attribute 4,7 (-mfp64 -mno-odd-spreg)
11 MIPS ABI Flags Version: 0
13 ISA: MIPS.*
attr-gnu-abi-fp-1.d 4 #name: MIPS gnu_attribute Tag_GNU_MIPS_ABI_FP,1
10 MIPS ABI Flags Version: 0
12 ISA: MIPS.*
attr-none-o32-fp64-nooddspreg.d 5 #name: MIPS infer fpabi (O32 fp64 nooddspreg)
11 MIPS ABI Flags Version: 0
13 ISA: MIPS.*
attr-none-o32-fp64.d 5 #name: MIPS infer fpabi (O32 fp64)
11 MIPS ABI Flags Version: 0
13 ISA: MIPS.*
attr-none-o32-fpxx.d 5 #name: MIPS infer fpabi (O32 fpxx)
11 MIPS ABI Flags Version: 0
13 ISA: MIPS.*
attr-none-single-float.d 5 #name: MIPS infer fpabi (single-precision)
11 MIPS ABI Flags Version: 0
13 ISA: MIPS.*
elf_ase_micromips-2.d 6 .*:.*file format.*mips.*
9 MIPS ABI Flags Version: 0
11 ISA: MIPS.*
elf_ase_mips16-2.d 6 .*:.*file format.*mips.*
9 MIPS ABI Flags Version: 0
11 ISA: MIPS.*
mipsr6@cache.d 2 #name: MIPS CACHE instruction
6 # Check MIPS CACHE instruction assembly.
8 .*: +file format .*mips.*
mipsr6@mips5-fp.d 2 #name: MIPS mips5 instructions
5 # Check MIPS V instruction assembly
7 .*: +file format .*mips.*
  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/
no-shared-1.ld 5 .MIPS.stubs : { *(.MIPS.stubs) }
  /external/llvm/lib/Target/Mips/
Mips16InstrInfo.cpp 35 : MipsInstrInfo(STI, Mips::Bimm16), RI() {}
67 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
68 Mips::GPR32RegClass.contains(SrcReg))
69 Opc = Mips::MoveR3216;
70 else if (Mips::GPR32RegClass.contains(DestReg) &&
71 Mips::CPU16RegsRegClass.contains(SrcReg))
72 Opc = Mips::Move32R16;
73 else if ((SrcReg == Mips::HI0) &&
74 (Mips::CPU16RegsRegClass.contains(DestReg)))
75 Opc = Mips::Mfhi16, SrcReg = 0
    [all...]
  /external/llvm/lib/Target/Mips/MCTargetDesc/
MipsNaClELFStreamer.cpp 1 //===-- MipsNaClELFStreamer.cpp - ELF Object Output for Mips NaCl ---------===//
10 // This file implements MCELFStreamer for Mips NaCl. It emits .o object files
20 #include "Mips.h"
27 #define DEBUG_TYPE "mips-mc-nacl"
31 const unsigned IndirectBranchMaskReg = Mips::T6;
32 const unsigned LoadStoreStackMaskReg = Mips::T7;
51 if (MI.getOpcode() == Mips::JALR) {
55 return MI.getOperand(0).getReg() == Mips::ZERO;
57 return MI.getOpcode() == Mips::JR;
62 && MI.getOperand(0).getReg() == Mips::SP)
    [all...]
  /external/llvm/test/MC/Mips/
module-softfloat.s 1 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 | \
4 # RUN: llvm-mc %s -arch=mips -mcpu=mips32 -filetype=obj -o - | \
5 # RUN: llvm-readobj -mips-abi-flags - | \
10 # Check if the MIPS.abiflags section was correctly emitted:
11 # CHECK-OBJ: MIPS ABI Flags {
  /external/valgrind/coregrind/m_gdbserver/
mips-linux.xml 10 <architecture>mips</architecture>
12 <xi:include href="mips-cpu.xml"/>
13 <xi:include href="mips-cp0.xml"/>
14 <xi:include href="mips-fpu.xml"/>
16 <feature name="org.gnu.gdb.mips.linux">
  /external/llvm/test/CodeGen/Mips/
adjust-callstack-sp.ll 1 ; RUN: llc < %s -march=mips -mattr=mips16 | FileCheck %s -check-prefix=M16
2 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32
3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32
4 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32
5 ; RUN: llc < %s -march=mips -mcpu=mips3 | FileCheck %s -check-prefix=GP64
6 ; RUN: llc < %s -march=mips -mcpu=mips64 | FileCheck %s -check-prefix=GP64
7 ; RUN: llc < %s -march=mips -mcpu=mips64r6 | FileCheck %s -check-prefix=GP64
  /external/llvm/test/CodeGen/Mips/Fast-ISel/
check-disabled-mcpus.ll 1 ; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \
3 ; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic \
5 ; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic \
8 ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
11 ; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic \
13 ; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic \
15 ; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic \
17 ; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic \
19 ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \
  /external/llvm/test/tools/llvm-readobj/
program-headers.test 5 RUN: llvm-readobj -program-headers %p/../../Object/Inputs/program-headers.mips \
6 RUN: | FileCheck %s -check-prefix ELF-MIPS
80 ELF-MIPS: Format: ELF32-mips
81 ELF-MIPS-NEXT: Arch: mips
82 ELF-MIPS-NEXT: AddressSize: 32bit
83 ELF-MIPS-NEXT: LoadName:
84 ELF-MIPS-NEXT: ProgramHeaders [
85 ELF-MIPS-NEXT: ProgramHeader
    [all...]

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