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  /external/valgrind/none/tests/mips32/
MoveIns.c 81 // mthc1 rt, fs
  /toolchain/binutils/binutils-2.25/opcodes/
ChangeLog 340 (dmtc1, mtc1, mthc1): Add COD attribute.
micromips-opc.c     [all...]
ChangeLog-0203 847 di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2,
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mips-opc.c     [all...]
  /art/compiler/utils/mips64/
assembler_mips64.cc 985 void Mips64Assembler::Mthc1(GpuRegister rt, FpuRegister fs) {
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  /external/v8/src/mips64/
assembler-mips64.cc 2532 void Assembler::mthc1(Register rt, FPURegister fs) { function in class:v8::internal::Assembler
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assembler-mips64.h     [all...]
simulator-mips64.cc     [all...]
  /external/llvm/test/MC/Disassembler/Mips/mips64r2/
valid-mips64r2.txt 236 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
  /external/llvm/test/MC/Disassembler/Mips/mips64r3/
valid-mips64r3.txt 234 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
  /external/llvm/test/MC/Disassembler/Mips/mips64r5/
valid-mips64r5.txt 233 0x44 0xe0 0x80 0x00 # CHECK: mthc1 $zero, $f16
  /external/v8/src/compiler/mips64/
code-generator-mips64.cc 187 __ mthc1(at, result_);
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  /external/v8/src/mips/
assembler-mips.h 853 void mthc1(Register rt, FPURegister fs);
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simulator-mips.cc     [all...]
  /external/v8/test/cctest/
test-assembler-mips.cc 424 __ mthc1(t1, f6);
426 __ mthc1(t3, f4);
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test-assembler-mips64.cc 426 __ mthc1(a5, f5);
876 __ mthc1(a5, f8); // f8 MS 32-bits.
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  /art/runtime/arch/mips64/
quick_entrypoints_mips64.S 715 mthc1 $t3, $\fpu
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  /toolchain/binutils/binutils-2.25/gas/
ChangeLog 606 MTHC1 when available. Check that correct code can be generated for
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  /toolchain/binutils/binutils-2.25/gas/config/
tc-mips.c     [all...]
  /external/valgrind/VEX/priv/
guest_mips_toIR.c     [all...]
  /art/runtime/interpreter/mterp/out/
mterp_mips.S 429 mthc1 AT, rlo; \
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mterp_mips64.S 239 mthc1 AT, \reg
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  /prebuilts/android-emulator/linux-x86_64/
emulator-mips 
  /prebuilts/android-emulator/linux-x86_64/qemu/linux-x86/
qemu-system-mips64el 

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