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  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/
ldst02.s 15 ld.s -1024(%r11),%r21
31 ld.s %r16(%r11),%r21
ldst03.s 19 ld.b -1023(%r11),%r21
35 ld.b %r16(%r11),%r21
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/
sh4a-dsp.d 22 0x00000016 4b e9 movua\.l @r11\+,r0
31 0x00000028 0b 3a stc sgr,r11
  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-cris/
tls-leie-18.d 39 80094: 41b2 moveq 1,\$r11
47 800a4: 5fbe 0c00 move.w 0xc,\$r11
  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-x86-64/
tlsgd8.dd 12 [ ]*[a-f0-9]+: 49 bb ([0-9a-f]{2} ){8} movabs \$0x[0-9a-f]+,%r11
16 [ ]*[a-f0-9]+: 4c 01 db add %r11,%rbx
tlsld3.dd 12 [ ]*[a-f0-9]+: 49 bb ([0-9a-f]{2} ){8} movabs \$0x[0-9a-f]+,%r11
16 [ ]*[a-f0-9]+: 4c 01 db add %r11,%rbx
tlsdesc-nacl.pd 14 +[0-9a-f]+: 4c 8b 1d .. .. .. .. mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x10>
16 +[0-9a-f]+: 4d 01 fb add %r15,%r11
17 +[0-9a-f]+: 41 ff e3 jmpq \*%r11
28 +[0-9a-f]+: 4c 8b 1d .. .. .. .. mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_DYNAMIC\+0x190>
30 +[0-9a-f]+: 4d 01 fb add %r15,%r11
31 +[0-9a-f]+: 41 ff e3 jmpq \*%r11
  /external/boringssl/src/crypto/bn/asm/
x86_64-mont.pl 71 $hi0="%r11";
113 mov %rsp,%r11
118 mov %r11,8(%rsp,$num,8) # tp[num+1]=%rsp
301 my @A=("%r10","%r11");
324 mov %rsp,%r11
329 mov %r11,8(%rsp,$num,8) # tp[num+1]=%rsp
733 my @A0=("%r10","%r11");
765 lea -64(%rsp,$num,4),%r11
767 sub $aptr,%r11
768 and \$4095,%r11
    [all...]
x86_64-mont5.pl 60 $hi0="%r11";
103 lea 2($num),%r11
104 neg %r11
105 lea (%rsp,%r11,8),%rsp # tp=alloca(8*(num+2))
116 mov %r10,%r11
118 and \$`$N/8-1`,%r11
122 lea 96($bp,%r11,8),$bp # pointer within 1st cache line
359 my @A=("%r10","%r11");
401 lea -64(%rsp,$num,2),%r11
402 sub $ap,%r11
    [all...]
  /external/llvm/test/CodeGen/X86/
preserve_allcc64.ll 68 call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{rbp},~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15}"()
72 ; Make sure only R11 is saved before the call
77 ;SSE: movq %r11, [[REG:%[a-z0-9]+]]
79 ;SSE: movq [[REG]], %r11
86 %a6 = call i64 asm sideeffect "", "={r11}"() nounwind
102 call void asm sideeffect "", "{rax},{rcx},{rdx},{r8},{r9},{r10},{r11},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},{xmm8},{xmm9},{xmm10},{xmm11},{xmm12},{xmm13},{xmm14},{xmm15}"(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, <2 x double> %a10, <2 x double> %a11, <2 x double> %a12, <2 x double> %a13, <2 x double> %a14, <2 x double> %a15, <2 x double> %a16, <2 x double> %a17, <2 x double> %a18, <2 x double> %a19, <2 x double> %a20, <2 x double> %a21, <2 x double> %a22, <2 x double> %a23)
  /external/llvm/test/MC/ARM/
eh-directive-integrated-test.s 36 .save {r4, r11, lr}
37 push {r4, r11, lr}
38 .setfp r11, sp, #4
39 add r11, sp, #4
44 sub sp, r11, #44
46 pop {r4, r11, pc}
  /external/v8/test/cctest/
test-disasm-ppc.cc 124 COMPARE(cmp(r5, r11), "7fa55800 cmp r5, r11");
126 COMPARE(cmp(r5, r11), "7f855800 cmp r5, r11");
145 COMPARE(stb(r5, MemOperand(r11, 11)), "98ab000b stb r5, 11(r11)");
  /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/
Syn_filt_32_neon.s 50 SUB r11, r5, #32 @ sig_lo[-16] address
59 VLD1.S16 {D8, D9, D10, D11}, [r11]! @ sig_lo[-16] ~ sig_lo[-1]
116 VMOV.S32 r11, D24[0] @r11 --- L_tmp >>= 4
118 SUB r12, r11, r10, LSL #12
119 @MOV r11, r12, ASR #16 @sig_lo[i]
Norm_Corr_neon.s 58 RSB r11, r4, #0 @k = -t_min
59 ADD r5, r0, r11, LSL #1 @get the &exc[k]
174 RSBLT r11, r5, #0
175 CLZLT r10, r11
180 MOV r11, r5, ASR #16 @corr = extract_h(L_tmp)
187 @r10 --- exp_corr, r11 --- corr
209 MUL r12, r6, r11
242 LDRSH r11, [r8] @ tmp = exc[k]
247 MUL r14, r11, r8
255 MUL r14, r11, r
    [all...]
  /system/core/libpixelflinger/
col32cb16blend_neon.S 44 push {r4-r11, lr} // stack ARM regs
122 and r11, r4, #0xff // extract red
125 mov r11, r11, lsl #5 // prescale red
136 smlabb r6, r6, r5, r11 // dest red * alpha + src red
150 pop {r4-r11, pc} // return
  /external/llvm/test/CodeGen/ARM/
debug-frame.ll 166 ; CHECK-FP: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
169 ; CHECK-FP: .cfi_offset r11, -8
177 ; CHECK-FP: add r11, sp, #28
178 ; CHECK-FP: .cfi_def_cfa r11, 8
184 ; CHECK-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
187 ; CHECK-FP-ELIM: .cfi_offset r11, -8
201 ; CHECK-V7-FP: push {r4, r10, r11, lr}
204 ; CHECK-V7-FP: .cfi_offset r11, -8
207 ; CHECK-V7-FP: add r11, sp, #8
208 ; CHECK-V7-FP: .cfi_def_cfa r11,
    [all...]
  /external/libhevc/common/arm/
ihevc_sao_edge_offset_class1_chroma.s 85 LDRH r11,[r3,r10] @pu1_src_top[wd - 2]
86 STRH r11,[r4] @*pu1_src_top_left = pu1_src_top[wd - 2]
87 ADD r11,r0,r10 @pu1_src[row * src_strd + wd - 2]
88 MOV r12,r2 @Move pu1_src_left pointer to r11
91 LDRH r10,[r11],r1 @Load pu1_src[row * src_strd + wd - 2]
125 SUBEQ r11,r0,r1 @pu1_src -= src_strd
126 MOVNE r11,r3 @*pu1_src_top
130 VLD1.8 D28,[r11]! @pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_strd)
131 VLD1.8 D29,[r11]! @pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_strd)
143 MOV r11,r9 @move ht to r11 for loop coun
    [all...]
ihevc_inter_pred_chroma_copy_w16out.s 115 and r11,r7,#6
116 cmp r11,#6
122 sub r11,r12,#4
157 sub r0,r5,r11
158 sub r1,r10,r11,lsl #1
193 @sub r11,r12,#8
195 rsb r11,r12,r3, lsl #2 @ r11 = (dst_strd * 4) - width
229 addle r1,r1,r11,lsl #1
273 addle r1,r1,r11,lsl #
    [all...]
  /external/valgrind/VEX/orig_ppc32/
date.orig 41 0x25471A68: 3960004B li r11,75
43 4: PUTL t2, R11
54 0x25471A70: 7D6903A6 mtctr r11
55 12: GETL R11, t8
375 0x25471B20: 7C0B0378 or r11,r0,r0
377 19: PUTL t12, R11
410 0x25471B3C: 2C0B0021 cmpi cr0,r11,33
411 39: GETL R11, t26
417 0x25471B40: 5560103A rlwinm r0,r11,2,0,29
418 44: GETL R11, t3
    [all...]
return0.orig 41 0x25471A68: 3960004B li r11,75
43 4: PUTL t2, R11
54 0x25471A70: 7D6903A6 mtctr r11
55 12: GETL R11, t8
375 0x25471B20: 7C0B0378 or r11,r0,r0
377 19: PUTL t12, R11
410 0x25471B3C: 2C0B0021 cmpi cr0,r11,33
411 39: GETL R11, t26
417 0x25471B40: 5560103A rlwinm r0,r11,2,0,29
418 44: GETL R11, t3
    [all...]
  /external/llvm/test/MC/Disassembler/ARM/
arm-tests.txt 115 # CHECK-NOT: pkhbtls r10, r11, r11, lsl #0
116 # CHECK: pkhbtls r10, r11, r11
206 # CHECK: uqadd16mi r6, r11, r8
248 # CHECK: stmiblo sp, {r0, r4, r8, r11, r12, pc}
251 # CHECK: ldmdb sp, {r0, r4, r8, r11, r12, pc}
281 # CHECK: str pc, [r11, #0]!
309 # CHECK: mrchs p2, #3, r11, c13, c6, #6
312 # CHECK: smlsldx r4, r12, r11, r
    [all...]
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/encoder/arm/armv5te/
vp8_packtokens_armv5.asm 129 ldrb r11, [r7, r4]
130 cmpge r11, #0xff
144 add r11, r4, #1 ; w->pos++
146 str r11, [r0, #vp8_writer_pos]
149 VALIDATE_POS r10, r11 ; validate_buffer at pos
227 ldrb r11, [r7, r4]
228 cmpge r11, #0xff
242 add r11, r4, #1 ; w->pos++
244 str r11, [r0, #vp8_writer_pos]
247 VALIDATE_POS r10, r11 ; validate_buffer at po
    [all...]
vp8_packtokens_mbrow_armv5.asm 150 ldrb r11, [r7, r4]
151 cmpge r11, #0xff
165 add r11, r4, #1 ; w->pos++
167 str r11, [r0, #vp8_writer_pos]
170 VALIDATE_POS r10, r11 ; validate_buffer at pos
248 ldrb r11, [r7, r4]
249 cmpge r11, #0xff
263 add r11, r4, #1 ; w->pos++
265 str r11, [r0, #vp8_writer_pos]
268 VALIDATE_POS r10, r11 ; validate_buffer at po
    [all...]
  /external/boringssl/win-x86_64/crypto/rc4/
rc4-x86_64.asm 33 mov r11,rsi
50 test r11,-16
57 sub r11,rbx
144 sub r11,8
150 test r11,-8
152 cmp r11,0
158 test r11,-32
162 sub r11,rbx
338 sub r11,16
340 test r11,-1
    [all...]
  /bionic/libc/arch-x86_64/string/
ssse3-strcmp-slm.S 32 /* Since the counter, %r11, is unsigned, we branch to strcmp_exitz
36 lea -16(%rcx, %r11), %r9; \
37 cmp %r9, %r11; \
41 mov %r9, %r11
87 mov %rdx, %r11
110 sub $16, %r11
187 sub $16, %r11
201 sub $16, %r11
261 sub $16, %r11
284 sub $16, %r11
    [all...]

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