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  /prebuilts/go/linux-x86/src/runtime/
signal_darwin_amd64.go 26 func (c *sigctxt) r11() uint64 { return c.regs().r11 } func
signal_linux_amd64.go 28 func (c *sigctxt) r11() uint64 { return c.regs().r11 } func
signal_nacl_amd64p32.go 28 func (c *sigctxt) r11() uint64 { return c.regs().r11 } func
sys_linux_arm64.s 239 MOVD fn+0(FP), R11
240 BL (R11)
313 MOVD gg+24(FP), R11
317 MOVD R11, -16(R1)
346 MOVD -16(RSP), R11 // g
351 CMP $0, R11
359 MOVD R10, g_m(R11)
360 MOVD R11, g
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/
cbitb_test.s 21 cbitb $3,[r12]0xa7a(r11,r10)
29 cbitb $3,[r13]0xa7a(r11,r10)
sbitb_test.s 21 sbitb $3,[r12]0xa7a(r11,r10)
29 sbitb $3,[r13]0xa7a(r11,r10)
tbitb_test.s 21 tbitb $3,[r12]0xa7a(r11,r10)
29 tbitb $3,[r13]0xa7a(r11,r10)
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/
rd-tls-1.d 24 [ ]+2c:[ ]+5fbd 0000 699a[ ]+move\.d \[\$?r11\+0\],\$?r9
30 [ ]+42:[ ]+2fbe 0000 0000[ ]+add\.d 0 <start>,\$?r11
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/
system.s 32 st.c %r11,%dirbase
53 flush -1024(%r11)
  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-cris/
tls-ldgde-14.d 51 80094: 41b2 moveq 1,\$r11
55 8009c: 5fbe 8c00 move\.w 0x8c,\$r11
tls-ldgde-15.d 51 80094: 41b2 moveq 1,\$r11
55 8009e: 6fbe 8c00 0000 move.d 8c <x2>,\$r11
tls-leie-19.d 46 80094: 41b2 moveq 1,\$r11
58 800ae: 6fbe 0c00 0000 move.d c <tls128\+0xc>,\$r11
  /toolchain/binutils/binutils-2.25/ld/testsuite/ld-powerpc/
vxworks1.dd 23 80830: 39 60 00 00 li r11,0
33 80850: 39 60 00 01 li r11,1
  /external/llvm/test/MC/ARM/
eh-directive-save.s 138 .save {r4, r5, r6, r7, r8, r9, r10, r11}
139 push {r4, r5, r6, r7, r8, r9, r10, r11}
140 pop {r4, r5, r6, r7, r8, r9, r10, r11}
194 .save {r4, r5, r6, r7, r8, r9, r10, r11, r14}
195 push {r4, r5, r6, r7, r8, r9, r10, r11, r14}
196 pop {r4, r5, r6, r7, r8, r9, r10, r11, r14}
224 .save {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
225 push {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
226 pop {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
238 .save {r4, r5, r6, r8, r9, r10, r11}
    [all...]
eh-compact-pr0.s 16 .save {r11, lr}
17 push {r11, lr}
18 .setfp r11, sp
19 mov r11, sp
20 pop {r11, lr}
30 .save {r11, lr}
31 push {r11, lr}
32 pop {r11, pc}
56 @ 0x9B = $sp can be found in $r11
57 @ 0x8480 = pop {r11, r14
    [all...]
  /external/libhevc/common/arm/
ihevc_itrans_recon_16x16.s 95 @ word32 r11 )
106 @ r11
119 @#define zero_rows r11
140 ldr r11,[sp,#56]
150 and r11,r11,r7
168 cmp r11,r7
171 cmp r11,#0xff00
182 cmp r11,#0xff00
194 cmp r11,#0xff0
    [all...]
  /art/runtime/arch/arm/
quick_entrypoints_arm.S 30 push {r4-r11, lr} @ 9 words (36 bytes) of callee saves.
39 .cfi_rel_offset r11, 28
69 push {r5-r8, r10-r11, lr} @ 7 words of callee saves
76 .cfi_rel_offset r11, 20
97 push {r5-r8, r10-r11, lr} @ 7 words of callee saves
104 .cfi_rel_offset r11, 20
124 pop {r5-r8, r10-r11, lr} @ 7 words of callee saves
130 .cfi_restore r11
145 push {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves and args.
155 .cfi_rel_offset r11, 3
    [all...]
  /external/libavc/encoder/arm/
ih264e_evaluate_intra16x16_modes_a9q.s 102 mov r11, #0
111 movne r11, #1
112 lsl r12, r11, #3
138 add r11, r11, #3
139 add r8, r10, r11
195 mov r11, #1
197 lsl r11 , #30
203 moveq r8, r11
207 moveq r9, r11
    [all...]
  /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/asm/internal/asm/
operand_test.go 142 {"R11", "R11"},
252 {"(R11)", "(R11)"},
265 {"R11", "R11"},
284 {"[R1-R12]", "[R1,R2,R3,R4,R5,R6,R7,R8,R9,g,R11,R12]"},
349 {"R11", "R11"},
427 {"R11", "R11"}
    [all...]
  /prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/asm/internal/asm/
operand_test.go 142 {"R11", "R11"},
252 {"(R11)", "(R11)"},
265 {"R11", "R11"},
284 {"[R1-R12]", "[R1,R2,R3,R4,R5,R6,R7,R8,R9,g,R11,R12]"},
349 {"R11", "R11"},
427 {"R11", "R11"}
    [all...]
  /external/llvm/test/CodeGen/SystemZ/
frame-16.ll 32 ; CHECK-FP: stc %r2, 4095(%r11)
50 ; CHECK-FP: stcy %r2, 4096(%r11)
71 ; CHECK-FP: stcy %r2, 524287(%r11)
93 ; CHECK-FP: stc %r2, 0(%r1,%r11)
114 ; CHECK-FP: stc %r2, 4095(%r1,%r11)
134 ; CHECK-FP: stcy %r2, 4096(%r1,%r11)
157 ; CHECK-FP: stcy %r2, 65535(%r1,%r11)
178 ; CHECK-FP: stc %r2, 7(%r1,%r11)
206 ; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)
231 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
    [all...]
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/ppc/
loopfilter_filters_altivec.asm 591 mfspr r11, 256 ;# get old VRSAVE
592 oris r12, r11, 0xffff
608 mtspr 256, r11 ;# reset old VRSAVE
619 mfspr r11, 256 ;# get old VRSAVE
620 oris r12, r11, 0xffff
634 mtspr 256, r11 ;# reset old VRSAVE
677 mfspr r11, 256 ;# get old VRSAVE
678 oris r12, r11, 0xffff
714 mtspr 256, r11 ;# reset old VRSAVE
770 mfspr r11, 256 ;# get old VRSAV
    [all...]
  /bionic/libm/x86_64/
s_cos.S 280 lea PI_INV_TABLE(%rip), %r11
281 addq %r11, %rcx
298 addq %r8, %r11
300 shrq $32, %r11
301 addq %r11, %r9
316 imulq %rax, %r11
324 addq %rdi, %r11
325 addq %r10, %r11
331 addq %r10, %r11
333 shrq $32, %r11
    [all...]
  /external/mesa3d/src/gallium/drivers/radeon/
AMDILISelLowering.cpp 580 // ilt r11, r1, 0
582 // iadd r1, r1, r11
584 // ixor r1, r1, r11
586 // ixor r10, r10, r11
603 // ilt r11, r1, 0
604 SDValue r11 = DAG.getSelectCC(DL, local
613 // iadd r1, r1, r11
614 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
619 // ixor r1, r1, r11
620 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
710 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT); local
    [all...]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
x86-64-specific-reg.l 212 .*:[0-9]*: Warning: .*r11.*rsi.*
213 .*:[0-9]*: Warning: .*r11.*rdi.*
214 .*:[0-9]*: Warning: .*r11.*rdi.*
215 .*:[0-9]*: Warning: .*r11.*rdi.*
216 .*:[0-9]*: Warning: .*r11.*rsi.*
217 .*:[0-9]*: Warning: .*r11.*rbx.*
218 .*:[0-9]*: Warning: .*r11.*rsi.*
219 .*:[0-9]*: Warning: .*r11.*rdi.*
220 .*:[0-9]*: Warning: .*r11.*rdi.*
221 .*:[0-9]*: Warning: .*r11.*rsi.
    [all...]

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