| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/fr30/ |
| allinsn.d | 27 e: ac ab sub r10,r11
54 24: 94 bc or r11,@r12
88 3c: 99 1b beorh 0x1,@r11
134 5c: b2 bc lsr r11,r12
162 7c: 05 ab lduh @r10,r11
182 98: 11 cb sth r11,@\(r13,r12\)
252 d0: 9f 0b jmp:d @r11
351 12a: 97 ab extsh r11
387 154: 8d 89 ldm1 \(r8,r11,r15\)
|
| /external/libavc/encoder/arm/ |
| ime_distortion_metrics_a9q.s | 570 stmfd sp!, {r4-r11, lr} @store register values to stack
582 mov r11, #15
617 subs r11, #1
666 ldr r11, [sp, #44]
670 vst1.32 {d0}, [r11]!
671 vst1.32 {d2}, [r11]!
672 vst1.32 {d4}, [r11]!
673 vst1.32 {d6}, [r11]!
675 ldmfd sp!, {r4-r11, pc} @Restoring registers from stack
962 @* Register Usage : R0-R11
[all...] |
| /external/boringssl/win-x86_64/crypto/aes/ |
| aes-x86_64.asm | 189 movzx r11d,BYTE[r11*1+r14]
594 movzx r11d,BYTE[r11*1+r14]
672 lea r11,[rcx*1+rcx]
676 and r11,rdi
680 xor r11,rdx
685 and r13,r11
691 lea r12,[r11*1+r11]
710 xor r11,rcx
727 xor r11,r1
[all...] |
| aesni-x86_64.asm | 523 mov r11,rcx
545 mov rcx,r11
572 mov rcx,r11
688 mov rcx,r11
711 movups xmm0,XMMWORD[r11]
717 mov rcx,r11
897 lea r11,[rcx]
906 movups xmm0,XMMWORD[r11]
911 movups xmm1,XMMWORD[16+r11]
914 movups xmm0,XMMWORD[32+r11]
[all...] |
| /external/bouncycastle/bcprov/src/main/java/org/bouncycastle/crypto/modes/gcm/ |
| GCMUtil.java | 112 int r10 = 0, r11 = 0, r12 = 0, r13 = 0; local
121 r11 ^= (r01 & m1);
134 x[1] = r11;
141 long r00 = x[0], r01 = x[1], r10 = 0, r11 = 0; local
150 r11 ^= (r01 & m1);
159 x[1] = r11;
|
| /external/libjpeg-turbo/simd/ |
| jsimd_mips_dspr2_asm.h | 150 r11 = 0, r12 = 0, r13 = 0, \
192 .if \r11 != 0
194 sw \r11, 40(sp)
225 r11 = 0, r12 = 0, r13 = 0, \
264 .if \r11 != 0
266 lw \r11, 40(sp)
|
| /external/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.td | 56 def R11 : AVRReg<11, "r11">, DwarfRegNum<[11]>;
101 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>;
123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| thumb-tests.txt | 54 # CHECK: mov r11, r7
146 # CHECK: stmdb sp, {r0, r2, r3, r8, r11, lr}
161 # CHECK: ldrd r3, r8, [r11, #-60]
290 # CHECK: smlad r5, r12, r8, r11
293 # CHECK: teq.w r0, r11
299 # CHECK: pldw [r11, r12, lsl #2]
|
| /external/opencv/cv/src/ |
| cvmatchcontours.cpp | 231 double match_v, d12, area1, area2, r11, r12, r21, r22, w1, w2; local
284 r11 = r12 = r21 = r22 = w1 = w2 = d12 = 0;
311 r11 = ptr11[j]->r1;
319 r11 = r21 = 0;
343 t0 = fabs( r11 * w1 + r21 * w2 );
348 t0 = fabs( r11 * w1 - r21 * w2 );
|
| /external/zlib/src/contrib/masmx64/ |
| inffasx64.asm | 29 ; rax, rcx, rdx, r8, r-9, r10, and r11, which are scratch.
52 mov r11, [rsp+72] ; /* r11 = dcode */
164 mov eax, [r11+r8*4] ; /* eax = dcode[hold & dmask] */
262 mov eax, [r11+rax*4] ; /* eax = dcode[val+(hold&mask[op])]*/
391 ; "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
|
| /external/libhevc/common/arm/ |
| ihevc_intra_pred_filters_luma_mode_11_to_17.s | 162 ldrb r11, [r1], #-1
170 strb r11, [r6], #1
226 ldrb r11, [r1], #-1
227 strb r11, [r6], #1
247 ldrb r11, [r1, r7, lsr #8]
248 strb r11, [r6], #-1
265 mov r11, r4 @col counter to be inc/dec by #8
404 subs r11, r11, #8
410 movle r11, r
[all...] |
| ihevc_sao_edge_offset_class1.s | 84 MOV r11,r2 @Move pu1_src_left pointer to r11
88 STRB r14,[r11],#1 @pu1_src_left[row]
138 MOV r11,r8 @move ht to r11 for loop count
213 SUBS r11,r11,#2 @II Decrement the ht loop count by 1
219 CMP r11,#1 @checking any residue remains
280 MOV r11,r8 @move ht to r11 for loop coun
[all...] |
| ihevc_inter_pred_chroma_vert_w16out.s | 266 rsb r11,r2,r2,lsl #3
268 add r14,r14,r11
280 rsble r11,r2,r2,lsl #3
299 pld [r0,r11]
304 add r11,r11,r2
315 cmp r11,r14
316 rsbgt r11,r2,r2,lsl #3
|
| ihevc_intra_pred_chroma_planar.s | 114 ldr r11, gau1_ihevc_planar_factor_addr @loads table of coeffs
116 add r11,r11,pc
154 add r12, r11, #1 @coeffs (to be reloaded after every row)
181 ldr r11, [r6], #-2 @src[2nt-1-row] (dec to take into account row)
185 vdup.s16 d3, r11 @src[2nt-1-row]
242 ldr r11, [r6], #-2 @src[2nt-1-row] (dec to take into account row)
244 vdup.s16 d3, r11 @src[2nt-1-row]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| frame-15.ll | 35 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r11)
62 ; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11)
89 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
116 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11)
143 ; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11)
170 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
199 ; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11)
227 ; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
255 ; CHECK-FP: lay %r1, 12296(%r11)
287 ; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
[all...] |
| alloca-01.ll | 52 ; CHECK-FP: lgr %r11, %r15
53 ; CHECK-FP: lmg %r6, %r15, 224(%r11)
|
| /system/extras/tests/memtest/ |
| bandwidth.h | 236 "stmfd sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12}\n"
247 "ldmia r0!, {r5, r6, r7, r8, r9, r10, r11, r12}\n"
248 "stmia r1!, {r5, r6, r7, r8, r9, r10, r11, r12}\n"
250 "ldmia r0!, {r5, r6, r7, r8, r9, r10, r11, r12}\n"
251 "stmia r1!, {r5, r6, r7, r8, r9, r10, r11, r12}\n"
259 "ldmfd sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12}\n"
549 "stmfd sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11}\n"
567 "mov r11, r4\n"
571 "stmia r0!, {r4, r5, r6, r7, r8, r9, r10, r11}\n"
578 "ldmfd sp!, {r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11}\n
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| opc-a.s | 24 add r11 = 0, r10
42 (p3) and r11 = -128, r12
45 or r11 = -128, r12
48 xor r11 = -128, r12
51 andcm r11 = -128, r12
56 shladd r11 = r30, 4, r31
61 shladdp4 r11 = r30, 4, r31
64 padd1.sss r11 = r30, r31
74 psub1.sss r11 = r30, r31
98 pshladd2 r10 = r11, 1, r1
[all...] |
| /development/ndk/platforms/android-21/arch-x86/include/asm/ |
| ptrace-abi.h | 55 #define R11 48
74 #define ARGOFFSET R11
|
| /development/ndk/platforms/android-21/arch-x86_64/include/asm/ |
| ptrace-abi.h | 55 #define R11 48
74 #define ARGOFFSET R11
|
| /development/ndk/platforms/android-9/arch-x86/include/asm/ |
| ptrace-abi.h | 55 #define R11 48
74 #define ARGOFFSET R11
|
| /external/clang/test/CXX/except/except.spec/ |
| p3.cpp | 49 extern void (*r11)() noexcept;
50 extern void (*r11)() noexcept(true);
|
| /external/llvm/lib/Target/BPF/ |
| BPFRegisterInfo.cpp | 40 Reserved.set(BPF::R11); // R11 is pseudo stack pointer
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.h | 27 // are still a few places that R11 and R10 are hard wired.
37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
|
| /external/llvm/lib/Target/XCore/ |
| XCoreCallingConv.td | 31 // The 'nest' parameter, if any, is passed in R11.
32 CCIfNest<CCAssignToReg<[R11]>>,
|
