| /external/llvm/test/CodeGen/PowerPC/ |
| extra-toc-reg-deps.ll | 70 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC0@toc@ha
72 ; CHECK: ld {{[0-9]+}}, .LC0@toc@l([[REG1]])
78 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC0@toc@ha
80 ; CHECK: ld {{[0-9]+}}, .LC0@toc@l([[REG1]])
|
| /external/v8/test/cctest/ |
| test-utils-arm64.h | 190 const Register& reg1);
|
| /external/vixl/test/ |
| test-utils-a64.h | 210 const Register& reg1);
|
| /art/compiler/utils/x86/ |
| assembler_x86.h | 485 void cmpl(Register reg0, Register reg1);
491 void testl(Register reg1, Register reg2);
493 void testl(Register reg1, const Address& address);
|
| /art/compiler/utils/x86_64/ |
| assembler_x86_64.cc | 1244 void X86_64Assembler::cmpl(CpuRegister reg0, CpuRegister reg1) {
1246 EmitOptionalRex32(reg0, reg1);
1248 EmitOperand(reg0.LowBits(), Operand(reg1));
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 89 unsigned Reg1, unsigned Reg2);
469 unsigned Reg1, unsigned Reg2) {
475 .addReg(Reg1)
|
| Thumb2SizeReduction.cpp | 659 unsigned Reg1 = MI->getOperand(1).getReg();
664 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
670 if (Reg1 != Reg0)
677 } else if (Reg0 != Reg1) {
[all...] |
| /external/vixl/src/vixl/a64/ |
| assembler-a64.cc | [all...] |
| macro-assembler-a64.cc | [all...] |
| assembler-a64.h | 410 bool AreAliased(const CPURegister& reg1,
423 // arguments. At least one argument (reg1) must be valid (not NoCPUReg).
424 bool AreSameSizeAndType(const CPURegister& reg1,
436 // arguments. At least one argument (reg1) must be valid (not NoVReg).
437 bool AreSameFormat(const VRegister& reg1,
445 // any subsequent arguments. At least one argument (reg1) must be valid
447 bool AreConsecutive(const VRegister& reg1,
456 explicit CPURegList(CPURegister reg1,
460 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
461 size_(reg1.size()), type_(reg1.type())
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-avr.c | 1144 unsigned int reg1 = 0; local
[all...] |
| tc-ia64.c | 3373 unsigned reg1, reg2; local
3778 int reg1, val; local
6114 int reg1, reg2; local
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| idct32x32_add_neon.asm | 72 ; reg1 = output[first_offset]
78 LOAD_FROM_OUTPUT $prev_offset, $first_offset, $second_offset, $reg1, $reg2
81 vld1.s16 {$reg1}, [r1]
84 ; (used) two registers ($reg1, $reg2)
88 ; output[first_offset] = reg1
94 STORE_IN_OUTPUT $prev_offset, $first_offset, $second_offset, $reg1, $reg2
97 vst1.16 {$reg1}, [r1]
241 DO_BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
276 vqrshrn.s32 $reg1, q8, #14
286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg
[all...] |
| /external/v8/src/ppc/ |
| macro-assembler-ppc.cc | [all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/ |
| vp9_idct32x32_add_neon.asm | 72 ; reg1 = output[first_offset]
78 LOAD_FROM_OUTPUT $prev_offset, $first_offset, $second_offset, $reg1, $reg2
81 vld1.s16 {$reg1}, [r1]
84 ; (used) two registers ($reg1, $reg2)
88 ; output[first_offset] = reg1
94 STORE_IN_OUTPUT $prev_offset, $first_offset, $second_offset, $reg1, $reg2
97 vst1.16 {$reg1}, [r1]
241 DO_BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
276 vqrshrn.s32 $reg1, q8, #14
286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg
[all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | [all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.h | 95 Register GetRegisterThatIsNotOneOf(Register reg1,
102 bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg,
230 void Swap(Register reg1, Register reg2, Register scratch = no_reg);
469 Register reg1,
[all...] |
| /external/v8/src/mips64/ |
| macro-assembler-mips64.h | 101 Register GetRegisterThatIsNotOneOf(Register reg1,
108 bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg,
258 void Swap(Register reg1, Register reg2, Register scratch = no_reg);
497 Register reg1,
[all...] |
| /external/elfutils/tests/ |
| run-addrcfi.sh | 34 integer reg1 (%ecx): undefined
81 integer reg1 (%ecx): undefined
133 integer reg1 (%rdx): undefined
199 integer reg1 (%rdx): undefined
303 integer reg1 (r1): location expression: call_frame_cfa stack_value
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| switch.ll | 374 ; CHECK: movq (%[[REG1:[a-z]+]]), %[[REG1]]
375 ; CHECK: movl 8(%[[REG1]]), %[[REG2:[a-z]+]]
|
| /external/libunwind_llvm/src/ |
| dwarf2.h | 157 DW_OP_reg1 = 0x51, // Contents of reg1
|
| /external/llvm/include/llvm/Support/ |
| Dwarf.def | 197 HANDLE_DW_OP(0x51, reg1)
|
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 140 unsigned Reg1 = MI->getOperand(Idx1).getReg();
153 if (HasDef && Reg0 == Reg1 &&
161 Reg0 = Reg1;
175 MI->getOperand(Idx2).setReg(Reg1);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 125 // Int Branch: 3 (opc, reg0, reg1)
|
| /external/v8/src/arm64/ |
| assembler-arm64.h | 339 Register GetAllocatableRegisterThatIsNotOneOf(Register reg1,
347 bool AreAliased(const CPURegister& reg1,
359 // arguments. At least one argument (reg1) must be valid (not NoCPUReg).
360 bool AreSameSizeAndType(const CPURegister& reg1,
377 explicit CPURegList(CPURegister reg1,
381 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
382 size_(reg1.SizeInBits()), type_(reg1.type()) {
383 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
[all...] |
