/external/llvm/test/Assembler/ |
2005-05-05-OpaqueUndefValues.ll | 5 @x = global %t undef
|
extractvalue-invalid-idx.ll | 8 extractvalue [0 x i32] undef, 0
|
extractvalue-no-idx.ll | 6 extractvalue <{ i32, i32 }> undef, !dbg !0
|
insertvalue-invalid-idx.ll | 7 insertvalue [0 x i32] undef, i32 0, 0
|
/external/llvm/test/CodeGen/AArch64/ |
arm64-2011-04-21-CPSRBug.ll | 8 %cmp = icmp eq i32* null, undef 10 store i8 %frombool, i8* undef, align 1 11 %tmp4 = load i8, i8* undef, align 1 19 br i1 undef, label %land.lhs.true14, label %if.end33
|
arm64-build-vector.ll | 14 %vset_lane = insertelement <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %conv, i32 0 30 %1 = insertelement <4 x float> undef, float %a, i32 0 42 %b = add <8 x i16> %a, <i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef> 43 %c = mul <8 x i16> %b, <i16 -20864, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef [all...] |
br-undef-cond.ll | 3 ; Make sure we don't end up with a CBNZ of an undef v-/phys-reg. 12 br i1 undef, label %0, label %.thread1880 14 %1 = icmp eq i32 undef, 0 16 %brmerge = or i1 %.not, undef
|
/external/llvm/test/CodeGen/AMDGPU/ |
subreg-eliminate-dead.ll | 9 %v0 = icmp eq <4 x i32> undef, <i32 0, i32 1, i32 2, i32 3> 13 %v6 = select i1 %v5, i32 undef, i32 0 14 %v15 = insertelement <2 x i32> undef, i32 %v6, i32 1 15 store <2 x i32> %v15, <2 x i32> addrspace(1)* undef, align 8
|
/external/llvm/test/CodeGen/ARM/ |
2009-08-15-RegScavengerAssert.ll | 6 tail call void @exit(i32 undef) noreturn nounwind
|
2011-08-12-vmovqqqq-pseudo.ll | 7 %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16.p0i8(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2) 8 store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, { <8 x i16>, <8 x i16>, <8 x i16> }* undef
|
2012-01-24-RegSequenceLiveRange.ll | 10 %tmp = load <2 x float>, <2 x float>* undef, align 8 12 %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0 21 %tmp12 = shufflevector <2 x i64> %tmp11, <2 x i64> undef, <1 x i32> zeroinitializer 23 %tmp14 = shufflevector <2 x float> %tmp13, <2 x float> undef, <4 x i32> zeroinitializer 25 %tmp16 = shufflevector <2 x i64> %tmp15, <2 x i64> undef, <1 x i32> zeroinitializer 28 tail call arm_aapcs_vfpcc void @bar(i8* undef, float %tmp18, float undef, float 0.000000e+00) nounwind 30 %tmp20 = shufflevector <2 x i64> %tmp19, <2 x i64> undef, <1 x i32> zeroinitializer 32 %tmp22 = shufflevector <2 x float> %tmp21, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> 34 %tmp24 = shufflevector <2 x i64> %tmp23, <2 x i64> undef, <1 x i32> zeroinitialize [all...] |
/external/llvm/test/CodeGen/PowerPC/ |
vsel-prom.ll | 8 br i1 undef, label %if.then, label %if.end 14 %0 = select i1 undef, <2 x double> undef, <2 x double> zeroinitializer 16 store double %1, double* undef, align 8
|
/external/llvm/test/CodeGen/SystemZ/ |
vec-move-11.ll | 1 ; Test insertions of register values into a nonzero index of an undef. 5 ; Test v16i8 insertion into an undef, with an arbitrary index. 10 %ret = insertelement <16 x i8> undef, i8 %val, i32 12 14 ; Test v16i8 insertion into an undef, with the first good index for VLVGP. 19 %ret = insertelement <16 x i8> undef, i8 %val, i32 7 23 ; Test v16i8 insertion into an undef, with the second good index for VLVGP. 28 %ret = insertelement <16 x i8> undef, i8 %val, i32 15 32 ; Test v8i16 insertion into an undef, with an arbitrary index. 37 %ret = insertelement <8 x i16> undef, i16 %val, i32 5 41 ; Test v8i16 insertion into an undef, with the first good index for VLVGP [all...] |
vec-move-12.ll | 1 ; Test insertions of memory values into a nonzero index of an undef. 5 ; Test v16i8 insertion into an undef, with an arbitrary index. 11 %ret = insertelement <16 x i8> undef, i8 %val, i32 12 15 ; Test v16i8 insertion into an undef, with the first good index for VLVGP. 21 %ret = insertelement <16 x i8> undef, i8 %val, i32 7 25 ; Test v16i8 insertion into an undef, with the second good index for VLVGP. 31 %ret = insertelement <16 x i8> undef, i8 %val, i32 15 35 ; Test v8i16 insertion into an undef, with an arbitrary index. 41 %ret = insertelement <8 x i16> undef, i16 %val, i32 5 45 ; Test v8i16 insertion into an undef, with the first good index for VLVGP [all...] |
/external/llvm/test/CodeGen/Thumb2/ |
2009-07-23-CPIslandBug.ll | 6 %0 = icmp eq i32 undef, 0 ; <i1> [#uses=1] 11 br i1 undef, label %bb86.preheader, label %bb7 18 br i1 undef, label %bb119, label %bb79 21 ret i32 undef
|
2009-08-10-ISelBug.ll | 5 store i32 undef, i32* undef, align 4 6 %0 = load [4 x i8]*, [4 x i8]** undef, align 4 ; <[4 x i8]*> [#uses=1] 7 %1 = load i8, i8* undef, align 1 ; <i8> [#uses=1]
|
/external/llvm/test/CodeGen/X86/ |
2012-07-15-broadcastfold.ll | 14 br i1 undef, label %work, label %exit 17 %A1 = insertelement <8 x float> undef, float %A0, i32 0 18 %A2 = shufflevector <8 x float> %A1, <8 x float> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> 22 ret <8 x float> undef
|
/external/llvm/test/Transforms/InstCombine/ |
2004-12-08-RemInfiniteLoop.ll | 4 %Y = srem i32 %X, undef ; <i32> [#uses=1]
|
/external/llvm/test/Transforms/InstSimplify/ |
2013-04-19-ConstantFoldingCrash.ll | 7 %a = and <2 x i64> undef, bitcast (<4 x i32> <i32 undef, i32 undef, i32 undef, i32 2147483647> to <2 x i64>)
|
/external/llvm/test/Transforms/JumpThreading/ |
2012-07-19-NoSuccessorIndirectBr.ll | 7 indirectbr i8* undef, []
|
/external/llvm/test/Transforms/SCCP/ |
2006-12-19-UndefBug.ll | 5 %X = and i1 false, undef ; <i1> [#uses=1]
|
/external/llvm/test/Verifier/ |
token6.ll | 5 ret token undef
|
token7.ll | 5 call token () undef ()
|
/external/opencv3/3rdparty/openexr/IlmImf/ |
OpenEXRConfig.h | 8 #undef HAVE_LINUX_PROCFS 15 #undef HAVE_DARWIN 23 #undef HAVE_COMPLETE_IOMANIP 30 #undef HAVE_LARGE_STACK
|
/external/opencv3/3rdparty/openexr/ |
OpenEXRConfig.h.cmakein | 8 #undef HAVE_LINUX_PROCFS 15 #undef HAVE_DARWIN 23 #undef HAVE_COMPLETE_IOMANIP 30 #undef HAVE_LARGE_STACK
|