| /external/v8/src/compiler/arm/ |
| code-generator-arm.cc | 699 __ vsub(i.OutputFloat32Register(), i.InputFloat32Register(0),
750 __ vsub(i.OutputFloat64Register(), i.InputFloat64Register(0),
[all...] |
| /external/llvm/test/CodeGen/Hexagon/ |
| v60Intrins.ll | 142 ; CHECK: v{{[0-9]*}}.b = vsub(v{{[0-9]*}}.b,v{{[0-9]*}}.b)
180 ; CHECK: v{{[0-9]*}}.h = vsub(v{{[0-9]*}}.h,v{{[0-9]*}}.h)
181 ; CHECK: v{{[0-9]*}}.h = vsub(v{{[0-9]*}}.h,v{{[0-9]*}}.h):{{[0-9]*}}sat
193 ; CHECK: v{{[0-9]*}}.ub = vsub(v{{[0-9]*}}.ub,v{{[0-9]*}}.ub):{{[0-9]*}}sat
206 ; CHECK: v{{[0-9]*}}.uh = vsub(v{{[0-9]*}}.uh,v{{[0-9]*}}.uh):{{[0-9]*}}sat
266 ; CHECK: v{{[0-9]*}}.w = vsub(v{{[0-9]*}}.w,v{{[0-9]*}}.w)
267 ; CHECK: v{{[0-9]*}}.w = vsub(v{{[0-9]*}}.w,v{{[0-9]*}}.w):{{[0-9]*}}sat
277 ; CHECK: v{{[0-9]*}}:{{[0-9]*}}.b = vsub(v{{[0-9]*}}:{{[0-9]*}}.b,v{{[0-9]*}}:{{[0-9]*}}.b)
296 ; CHECK: v{{[0-9]*}}:{{[0-9]*}}.h = vsub(v{{[0-9]*}}.ub,v{{[0-9]*}}.ub)
297 ; CHECK: v{{[0-9]*}}:{{[0-9]*}}.h = vsub(v{{[0-9]*}}:{{[0-9]*}}.h,v{{[0-9]*}}:{{[0-9]*}}.h
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| neon-cov.s | 281 regs3_if_64 vsub vsubq
|
| vfp1xD.d | 27 0+044 <[^>]*> ee300a40 (vsub\.f32|fsubs) s0, s0, s0
|
| vfp1xD_t2.d | 27 0+044 <[^>]*> ee30 0a40 (vsub\.f32|fsubs) s0, s0, s0
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| r5900-full-vu0.d | 126 [0-9a-f]+ <[^>]*> 4be0faac vsub\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf0xyzw
|
| r5900-error-vu0.s | 675 vsub.z $vf0z, $vf31z, $vf0x
|
| r5900-error-vu0.l | [all...] |
| /external/v8/src/arm/ |
| assembler-arm.h | [all...] |
| simulator-arm.cc | [all...] |
| assembler-arm.cc | 3074 void Assembler::vsub(const DwVfpRegister dst, function in class:v8::internal::Assembler
3094 void Assembler::vsub(const SwVfpRegister dst, const SwVfpRegister src1, function in class:v8::internal::Assembler
[all...] |
| macro-assembler-arm.h | 487 // vadd and vsub generate the Canonical NaN (if a NaN must be generated).
[all...] |
| /external/v8/test/cctest/ |
| test-assembler-arm.cc | 1061 __ vsub(d25, d25, d18);
1175 __ vsub(d2, d0, d1);
[all...] |
| /external/boringssl/linux-arm/crypto/aes/ |
| aesv8-armx32.S | 105 vsub.i8 q2,q2,q10 @ adjust the mask
|
| /external/llvm/lib/Target/ARM/ |
| ARMScheduleSwift.td | 591 (instregex "VADD(S|f)", "VSUB(S|f)", "VABD", "VPADDf", "VMAX", "VMIN", "VPMAX",
[all...] |
| ARMInstrNEON.td | [all...] |
| ARMInstrVFP.td | 301 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
307 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
[all...] |
| /art/disassembler/ |
| disassembler_arm.cc | 883 // VMLA, VMLS, VMUL, VNMUL, VADD, VSUB, VDIV, VMOV, ...
896 // |1110|1110|0|D|11| Vn | Vd |101|S|N|1|M|0| Vm | VSUB
912 opcode << (Q == 0 ? "vadd" : "vsub") << (S != 0 ? ".f64" : ".f32");
[all...] |
| /external/valgrind/none/tests/arm/ |
| neon128.stdout.exp | 106 ---- VSUB ----
107 vsub.i32 q0, q1, q2 :: Qd 0xffffffa0 0xffffffa0 0xffffffa0 0xffffffa0 Qm (i32)0x00000018 Qn (i32)0x00000078
108 vsub.i64 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
109 vsub.i32 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
110 vsub.i16 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
111 vsub.i8 q0, q1, q2 :: Qd 0x00000014 0x00000014 0x00000014 0x00000014 Qm (i32)0x0000008c Qn (i32)0x00000078
112 vsub.i8 q0, q1, q2 :: Qd 0x000000ff 0x000000ff 0x000000ff 0x000000ff Qm (i32)0x80000001 Qn (i32)0x80000002
113 vsub.i16 q0, q1, q2 :: Qd 0x0000ffff 0x0000ffff 0x0000ffff 0x0000ffff Qm (i32)0x80000001 Qn (i32)0x80000002
114 vsub.i32 q0, q1, q2 :: Qd 0xffffffff 0xffffffff 0xffffffff 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80000002
115 vsub.i64 q0, q1, q2 :: Qd 0xfffffffe 0xffffffff 0xfffffffe 0xffffffff Qm (i32)0x80000001 Qn (i32)0x80 (…)
[all...] |
| /external/boringssl/src/crypto/aes/asm/ |
| aesv8-armx.pl | 173 vsub.i8 $mask,$mask,$key // adjust the mask
|
| /external/llvm/test/CodeGen/ARM/ |
| fp16-promote.ll | 30 ; CHECK-VFP: vsub.f32
|
| /external/valgrind/VEX/priv/ |
| host_arm_defs.c | 739 case ARMneon_VSUB: return "vsub";
740 case ARMneon_VSUBFP: return "vsub";
[all...] |
| /external/libavc/common/arm/ |
| ih264_deblk_chroma_a9.s | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXVector.td | 316 defm VSub : IntBinVOp<"sub.s", sub, SUBi64rr, SUBi32rr, SUBi16rr, SUBi8rr>;
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| metag.h | [all...] |
