| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCTargetDesc.cpp | 87 CodeGenOpt::Level OL) {
98 X->initMCCodeGenInfo(RM, CM, OL);
105 CodeGenOpt::Level OL) {
120 X->initMCCodeGenInfo(RM, CM, OL);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZTargetMachine.h | 33 CodeGenOpt::Level OL);
|
| SystemZTargetMachine.cpp | 86 CodeGenOpt::Level OL)
88 RM, CM, OL),
|
| /external/llvm/lib/Target/X86/ |
| X86TargetMachine.h | 34 CodeModel::Model CM, CodeGenOpt::Level OL);
|
| X86TargetMachine.cpp | 108 CodeGenOpt::Level OL)
110 OL),
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUTargetMachine.h | 45 CodeGenOpt::Level OL);
|
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCTargetDesc.cpp | 56 CodeGenOpt::Level OL) {
58 X->initMCCodeGenInfo(RM, CM, OL);
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCTargetDesc.cpp | 58 CodeGenOpt::Level OL) {
60 X->InitMCCodeGenInfo(RM, CM, OL);
|
| /external/llvm/lib/Target/Mips/ |
| MipsTargetMachine.cpp | 89 CodeGenOpt::Level OL, bool isLittle)
91 CPU, FS, Options, RM, CM, OL),
111 CodeGenOpt::Level OL)
112 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
120 CodeGenOpt::Level OL)
121 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXTargetMachine.cpp | 94 CodeGenOpt::Level OL, bool is64bit)
96 CM, OL),
114 CodeGenOpt::Level OL)
115 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
123 CodeGenOpt::Level OL)
124 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
|
| /external/llvm/lib/Target/ |
| TargetMachineC.cpp | 135 CodeGenOpt::Level OL;
138 OL = CodeGenOpt::None;
141 OL = CodeGenOpt::Less;
144 OL = CodeGenOpt::Aggressive;
147 OL = CodeGenOpt::Default;
153 CM, OL));
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetMachine.cpp | 127 CodeGenOpt::Level OL,
132 Options, RM, CM, OL),
169 CodeGenOpt::Level OL)
170 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
177 CodeGenOpt::Level OL)
178 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
|
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| AMDGPUMCTargetDesc.cpp | 62 CodeGenOpt::Level OL) {
64 X->initMCCodeGenInfo(RM, CM, OL);
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyTargetMachine.cpp | 47 CodeGenOpt::Level OL)
50 TT, CPU, FS, Options, RM, CM, OL),
|
| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| XCoreMCTargetDesc.cpp | 68 CodeGenOpt::Level OL) {
79 X->initMCCodeGenInfo(RM, CM, OL);
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUTargetMachine.cpp | 108 CodeModel::Model CM, CodeGenOpt::Level OL)
109 : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
118 CodeModel::Model CM, CodeGenOpt::Level OL)
119 : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
|
| /external/llvm/lib/CodeGen/ |
| LiveDebugValues.cpp | 243 auto OL = OutLocs.find(CurMBB);
244 assert(OL != OutLocs.end());
245 VarLocList &VLL = OL->second;
284 auto OL = OutLocs.find(p);
286 if (OL == OutLocs.end())
291 InLocsT = OL->second;
296 VarLocList &VLL = OL->second;
|
| LLVMTargetMachine.cpp | 79 CodeGenOpt::Level OL)
81 CodeGenInfo = T.createMCCodeGenInfo(TT.str(), RM, CM, OL);
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCTargetDesc.cpp | 78 CodeGenOpt::Level OL) {
103 X->initMCCodeGenInfo(RM, CM, OL);
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCTargetDesc.cpp | 87 CodeGenOpt::Level OL) {
93 X->initMCCodeGenInfo(RM, CM, OL);
|
| /external/llvm/include/llvm/Support/ |
| TargetRegistry.h | 98 CodeGenOpt::Level OL);
108 CodeGenOpt::Level OL);
307 CodeGenOpt::Level OL) const {
310 return MCCodeGenInfoCtorFn(Triple(TT), RM, CM, OL);
365 CodeGenOpt::Level OL = CodeGenOpt::Default) const {
369 CM, OL);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonTargetMachine.cpp | 128 CodeGenOpt::Level OL)
131 "n16:32", TT, CPU, FS, Options, RM, CM, OL),
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCTargetDesc.cpp | 165 CodeGenOpt::Level OL) {
169 X->initMCCodeGenInfo(RM, CM, OL);
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 92 CodeGenOpt::Level OL) {
106 X->initMCCodeGenInfo(RM, CM, OL);
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 157 CodeGenOpt::Level OL) {
200 X->initMCCodeGenInfo(RM, CM, OL);
|
