| /external/libhevc/common/arm/ |
| ihevc_itrans_recon_8x8.s | 134 @// row 1 first half - d6 - y1
190 vld1.16 d6,[r0]!
192 vmull.s16 q12,d6,d0[1] @// y1 * cos1(part of b0)
194 vmull.s16 q13,d6,d0[3] @// y1 * cos3(part of b1)
196 vmull.s16 q14,d6,d1[1] @// y1 * sin3(part of b2)
198 vmull.s16 q15,d6,d1[3] @// y1 * sin1(part of b3)
218 @// vld1.16 d6,[r0]!
271 vqrshrn.s32 d6,q14,#shift_stage1_idct @// r1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
289 vld1.16 d6,[r0]!
302 vmull.s16 q12,d6,d0[1] @// y1 * cos1(part of b0
[all...] |
| ihevc_padding.s | 146 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
147 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
148 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
149 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
150 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
265 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
266 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
267 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
268 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes store
269 vst1.8 {d6,d7},[r7]! @128/8 = 16 bytes stor
[all...] |
| ihevc_inter_pred_chroma_vert.s | 153 vqrshrun.s16 d6,q3,#6 @shifts right
157 vst1.8 {d6},[r1]! @stores the loaded value
182 vld1.32 {d6[0]},[r0] @vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp1, 0
185 vld1.32 {d6[1]},[r6],r2 @loads pu1_src_tmp
186 vdup.32 d7,d6[1]
191 vmlsl.u8 q2,d6,d0
231 vld1.8 {d6},[r6],r2 @load and increment
236 vmlal.u8 q15,d6,d2
240 vmull.u8 q14,d6,d1 @mul_res 2
252 vmlsl.u8 q13,d6,d
[all...] |
| ihevc_intra_pred_chroma_mode2.s | 132 vld2.8 {d6,d7},[r10],r8
151 vrev64.8 d22,d6
192 vld2.8 {d6,d7},[r10],r8
215 vrev64.8 d22,d6
281 vshl.i64 d6,d18,#32
285 vrev64.8 d6,d6
289 vzip.8 d6,d7
290 vst1.8 {d6},[r2],r3
|
| ihevc_inter_pred_chroma_vert_w16out.s | 182 vld1.32 {d6[0]},[r0] @vld1_lane_u32((uint32_t *)pu1_src_tmp, src_tmp1, 0
185 vld1.32 {d6[1]},[r6],r2 @loads pu1_src_tmp
186 vdup.32 d7,d6[1]
191 vmlsl.u8 q2,d6,d0
231 vld1.8 {d6},[r6],r2 @load and increment
236 vmlal.u8 q15,d6,d2
240 vmull.u8 q14,d6,d1 @mul_res 2
251 vmlsl.u8 q13,d6,d0
262 vld1.8 {d6},[r6],r2 @load and increment
279 vmlal.u8 q15,d6,d
[all...] |
| ihevc_intra_pred_filters_luma_mode_11_to_17.s | 287 vmovn.s16 d6, q11
304 vand d6, d6, d29 @fract values in d1/ idx values in d0
313 vsub.s8 d7, d28, d6 @32-fract
321 vmlal.u8 q12, d13, d6 @mul (row 0)
331 vmlal.u8 q11, d17, d6 @mul (row 1)
342 vmlal.u8 q10, d15, d6 @mul (row 2)
353 vmlal.u8 q9, d11, d6 @mul (row 3)
364 vmlal.u8 q12, d13, d6 @mul (row 4)
375 vmlal.u8 q11, d17, d6 @mul (row 5
[all...] |
| ihevc_intra_pred_chroma_mode_3_to_9.s | 168 vmovn.s16 d6, q11
184 vand d6, d6, d29 @fract values in d1/ idx values in d0
198 vsub.s8 d7, d28, d6 @32-fract
208 vmlal.u8 q12, d13, d6 @mul (row 0)
218 vmlal.u8 q11, d17, d6 @mul (row 1)
229 vmlal.u8 q10, d15, d6 @mul (row 2)
240 vmlal.u8 q9, d11, d6 @mul (row 3)
251 vmlal.u8 q12, d13, d6 @mul (row 4)
264 vmlal.u8 q11, d17, d6 @mul (row 5
[all...] |
| ihevc_intra_pred_luma_mode2.s | 134 vld1.8 {d6},[r0],r8
152 vrev64.8 d14,d6
192 vld1.8 {d6},[r0],r8
216 vrev64.8 d14,d6
248 vld1.8 {d6},[r10]
258 vrev64.8 d7,d6
|
| ihevc_intra_pred_luma_mode_18_34.s | 142 vld1.8 {d6},[r8],r6
169 vst1.8 {d6},[r10],r3
179 vld1.8 {d6},[r8],r6
208 vst1.8 {d6},[r10],r3
218 vld1.8 {d6},[r8],r6
239 vst1.8 {d6},[r10],r3
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.S | 41 VLD1.8 {d6,d7},[r0],r1
48 VMLAL.U8 q9,d6,d31
49 VMLAL.U8 q10,d6,d31
67 VADDL.U8 q12,d6,d16
68 VMLSL.U8 q11,d6,d30
113 VEXT.8 d29,d25,d6,#2
124 VQRSHRUN.S32 d6,q3,#10
128 VQMOVN.U16 d6,q3
|
| omxVCM4P10_PredictIntraChroma_8x8_s.S | 76 VMOV.I8 d6,#0x4
78 VSHR.U64 d6,d6,#32
79 VADD.I8 d6,d6,d5
81 VTBL.8 d4,{d1-d2},d6
144 VLD1.8 {d6[]},[r0],r10
170 VEXT.8 d9,d4,d6,#2
190 VDUP.16 q0,d6[0]
191 VDUP.16 q1,d6[1
[all...] |
| armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.S | 59 VMLS.I16 d6,d16,d30
63 VMLA.I16 d6,d18,d31
67 VQRSHRUN.S16 d6,q3,#5
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| ual-vcmp.s | 20 vcmpe.f64 d6, #0.00
|
| neon-psyn.s | 37 moo .dn d6
50 el2 .dn d6.16[1]
65 vld3 {d2.s16[1], d4.s16[1], d6.s16[1]}, [r10]
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68k/ |
| mcf-mov3q.d | 16 e: ad76 6803 mov3ql #6,%fp@\(0+03,%d6:l\)
|
| mcf-mac.s | [all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/rx/ |
| sccnd.d | 55 92: fc d6 02 fe 7f scc\.w 65532\[r0\]
56 97: fc d6 f2 fe 7f scc\.w 65532\[r15\]
72 d6: fc d5 f2 7e scc\.w 252\[r15\]
73 da: fc d6 02 fe 7f scc\.w 65532\[r0\]
74 df: fc d6 f2 fe 7f scc\.w 65532\[r15\]
91 122: fc d6 00 fe 7f sceq\.w 65532\[r0\]
92 127: fc d6 f0 fe 7f sceq\.w 65532\[r15\]
109 16a: fc d6 00 fe 7f sceq\.w 65532\[r0\]
110 16f: fc d6 f0 fe 7f sceq\.w 65532\[r15\]
127 1b2: fc d6 04 fe 7f scgtu\.w 65532\[r0\
[all...] |
| /external/libpng/arm/ |
| filter_neon.S | 69 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
72 vadd.u8 d2, d1, d6
91 vext.8 d6, d22, d23, #6
96 vadd.u8 d2, d1, d6
124 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
131 vadd.u8 d2, d2, d6
155 vext.8 d6, d22, d23, #6
165 vadd.u8 d2, d2, d6
197 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
204 vadd.u8 d2, d2, d6
[all...] |
| /external/opencv3/3rdparty/libpng/arm/ |
| filter_neon.S | 44 vld4.32 {d4[],d5[],d6[],d7[]}, [r1]
47 vadd.u8 d2, d1, d6
66 vext.8 d6, d22, d23, #6
71 vadd.u8 d2, d1, d6
99 vld4.32 {d4[],d5[],d6[],d7[]}, [r1]
106 vadd.u8 d2, d2, d6
130 vext.8 d6, d22, d23, #6
140 vadd.u8 d2, d2, d6
172 vld4.32 {d4[],d5[],d6[],d7[]}, [r1]
179 vadd.u8 d2, d2, d6
[all...] |
| /external/llvm/test/MC/ARM/ |
| neon-vld-encoding.s | 12 vld1.16 {d4, d5, d6}, [r3:64]
13 vld1.32 {d5, d6, d7}, [r3]
14 vld1.64 {d6, d7, d8}, [r3:64]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
17 vld1.32 {d5, d6, d7, d8}, [r3]
18 vld1.64 {d6, d7, d8, d9}, [r3:64]
39 vld1.16 {d4, d5, d6}, [r3:64]!
40 vld1.32 {d5, d6, d7}, [r3]!
41 vld1.64 {d6, d7, d8}, [r3:64]!
44 vld1.16 {d4, d5, d6}, [r3:64], r
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/neon/ |
| vp8_subpixelvariance16x16_neon.asm | 54 vld1.u8 {d5, d6, d7}, [r0], r1
73 vmull.u8 q10, d6, d0
80 vext.8 d5, d5, d6, #1
90 vext.8 d6, d6, d7, #1
95 vmlal.u8 q10, d6, d1
111 vld1.u8 {d5, d6, d7}, [r0], r1
126 vmull.u8 q12, d6, d0
131 vext.8 d5, d5, d6, #1
139 vext.8 d6, d6, d7, #
[all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_Resize.S | 44 * and accumulate them by the coefficients in d6[0..3], leaving the results in
63 vmull.u16 q12, d18, d6[1]
64 vmull.u16 q13, d19, d6[1]
65 vmlsl.u16 q12, d16, d6[0]
66 vmlsl.u16 q13, d17, d6[0]
67 vmlal.u16 q12, d20, d6[2]
68 vmlal.u16 q13, d21, d6[2]
69 vmlsl.u16 q12, d22, d6[3]
70 vmlsl.u16 q13, d23, d6[3]
91 vmull.u16 q12, d18, d6[1
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| rtm-intel.d | 19 [ ]*[a-f0-9]+: 0f 01 d6 xtest
|
| rtm.d | 18 [ ]*[a-f0-9]+: 0f 01 d6 xtest
|
| x86-64-rtm.d | 18 [ ]*[a-f0-9]+: 0f 01 d6 xtest
|
