| /external/libhevc/common/arm/ |
| ihevc_inter_pred_chroma_copy_w16out.s | 107 stmfd sp!, {r4-r12, r14} @stack stores the values of the arguments
108 ldr r12,[sp,#48] @loads wd
109 lsl r12,r12,#1 @2*wd
118 tst r12,#7 @conditional check for wd (multiples)
122 sub r11,r12,#4
128 subs r4,r12,#0 @wd conditional subtract
165 ldmfd sp!,{r4-r12,r15} @reload the registers from sp
169 subs r4,r12,#0 @wd conditional subtract
193 @sub r11,r12,#
[all...] |
| ihevc_deblk_luma_vert.s | 62 push {r3-r12,lr}
120 ldrb r12,[r0,#0] @ 0 value
125 add r12,r12,r2
126 subs r9,r12,r9,lsl #1 @ dq0 value is stored in r9
148 ldrb r12,[r14,#0] @ 0 value
155 add r12,r12,r4
156 subs r12,r12,r3,lsl #1 @ dq3value is stored in r1
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| x86-64-tbm.s | 39 BLCFILL (%rsi,%r12,4),%edx
60 BLCFILL 0xA(%r12,%r12,1),%rdx
61 BLCFILL %r14,%r12
65 BLCFILL (%r12,%rsi),%rsp
91 BLCI %r12,%rcx
101 BLCI (%r12),%rdx
132 BLCIC 0xDEAD(%r10,%r10,1),%r12
148 BLCMSK (%r12,%rdx),%esp
150 BLCMSK 0x0(,%r13d),%r12
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/ppc/ |
| filter_bilinear_altivec.asm | 36 li r12, 32
64 ;# r12 32
169 oris r12, r11, 0xf830
170 ori r12, r12, 0xfff8
171 mtspr 256, r12 ;# set VRSAVE
178 load_c v10, b_0123_b, 0, r9, r12
179 load_c v11, b_4567_b, 0, r9, r12
254 oris r12, r11, 0xf830
255 ori r12, r12, 0xfff
[all...] |
| variance_subpixel_altivec.asm | 25 load_c \V0, vfilter_b, r6, r12, r10
45 load_c v20, hfilter_b, r5, r12, r0
49 load_c v28, b_hperm_b, 0, r12, r0
52 li r12, 32
67 ;# r12 32
196 oris r12, r11, 0xf830
197 ori r12, r12, 0xfff8
198 mtspr 256, r12 ;# set VRSAVE
205 load_c v10, b_0123_b, 0, r12, r
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/crx/ |
| misc_insn.d | 28 18: 08 30 cd 60 macsd r12, r13
55 3c: 08 30 ce 30 sextbw r12, r14
88 64: 08 30 dc 82 maxub r13, r12
124 94: 08 30 2c 8e cntlsb r2, r12
133 a0: 08 30 dc 92 maxuw r13, r12
169 d0: 08 30 2c 9e cntlsw r2, r12
178 dc: 08 30 dc a2 maxud r13, r12
214 10c: 08 30 2c ae cntlsd r2, r12
221 114: 61 3e ec 21 ram \$0x18, \$0x9, \$0x1, r14, r12
|
| arith_insn.s | 23 addcb r11 , r12
51 subb $07 , r12
76 adduw $32767 , r12
101 cmpw r12 , r13
125 subcw r11 , r12
158 addcd r11 , r12
190 subd $07 , r12
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.S | 30 PUSH {r4-r12,lr}
32 ADD r12,r0,r1,LSL #2
35 VLD1.8 {d10,d11},[r12],r1
37 VLD1.8 {d12,d13},[r12],r1
45 VLD1.8 {d14,d15},[r12],r1
47 VLD1.8 {d16,d17},[r12],r1
129 POP {r4-r12,pc}
|
| omxVCM4P10_FilterDeblockingLuma_VerEdge_I_s.S | 30 PUSH {r4-r12,lr}
45 LDRH r12,[r4],#4
46 CMP r12,#0
74 TST r12,#0xff
79 TST r12,#0xff00
85 TST r12,#4
167 POP {r4-r12,pc}
|
| armVCM4P10_Interpolate_Chroma_s.S | 42 PUSH {r4-r12,lr}
54 SMULBB r12,r8,r9
59 VDUP.8 d12,r12
103 POP {r4-r12,pc}
126 POP {r4-r12,pc}
149 POP {r4-r12,pc}
162 POP {r4-r12,pc}
173 POP {r4-r12,pc}
184 POP {r4-r12,pc}
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/ |
| a2.d | 91 fc: (7d 6a 61 f8|f8 61 6a 7d) bpermd r10,r11,r12
93 104: (7d 6a 63 f8|f8 63 6a 7d) cmpb r10,r11,r12
121 174: (7d 4b 62 7e|7e 62 4b 7d) dcbtep r10,r11,r12
126 188: (7d 4b 61 fe|fe 61 4b 7d) dcbtstep r10,r11,r12
156 200: (7d 4b 66 66|66 66 4b 7d) erativax r10,r11,r12
159 20c: (7d 4b 61 27|27 61 4b 7d) eratsx\. r10,r11,r12
160 210: (7d 4b 61 26|26 61 4b 7d) eratsx r10,r11,r12
275 3dc: (7d 4b 63 2d|2d 63 4b 7d) icswx\. r10,r11,r12
276 3e0: (7d 4b 63 2c|2c 63 4b 7d) icswx r10,r11,r12
277 3e4: (7d 4b 65 de|de 65 4b 7d) isel r10,r11,r12,2
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| sad_media.asm | 25 stmfd sp!, {r4-r12, lr}
47 ldr r12, [r2, #0x8] ; load 4 ref pixels (1B)
56 usada8 r4, r10, r12, r4 ; calculate sad for 4 pixels
72 ldr r12, [r2, #0x8] ; load 4 ref pixels (2B)
78 usada8 r4, r10, r12, r4 ; calculate sad for 4 pixels
90 ldmfd sp!, {r4-r12, pc}
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/armv6/ |
| vp8_sad16x16_armv6.asm | 26 stmfd sp!, {r4-r12, lr}
48 ldr r12, [r2, #0x8] ; load 4 ref pixels (1B)
57 usada8 r4, r10, r12, r4 ; calculate sad for 4 pixels
73 ldr r12, [r2, #0x8] ; load 4 ref pixels (2B)
79 usada8 r4, r10, r12, r4 ; calculate sad for 4 pixels
91 ldmfd sp!, {r4-r12, pc}
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/ |
| rd-pic-1.s | 22 move.d [r5+extsym6:GOT-110],r12
23 move.d [r9=r5+extsym6:GOT-220],r12
29 sub.d [r12+extsym3:GOT16-156],r9,r8
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/ |
| fldst01.d | 24 38: 06 fe 8c 25 fld.l -508\(%r12\),%f12
41 7c: 07 fe 8e 25 fld.l -508\(%r12\)\+\+,%f14
51 a4: 02 60 f9 20 fld.l %r12\(%r7\),%f25
56 b8: 02 88 94 21 fld.l %r17\(%r12\),%f20
66 e0: 03 60 e7 20 fld.l %r12\(%r7\)\+\+,%f7
71 f4: 03 88 8c 21 fld.l %r17\(%r12\)\+\+,%f12
|
| fldst02.d | 24 38: 00 fe 84 25 fld.d -512\(%r12\),%f4
41 7c: 01 fe 9c 25 fld.d -512\(%r12\)\+\+,%f28
51 a4: 00 60 f2 20 fld.d %r12\(%r7\),%f18
56 b8: 00 88 88 21 fld.d %r17\(%r12\),%f8
66 e0: 01 60 ee 20 fld.d %r12\(%r7\)\+\+,%f14
71 f4: 01 88 98 21 fld.d %r17\(%r12\)\+\+,%f24
|
| fldst03.d | 24 38: 04 fe 88 25 fld.q -512\(%r12\),%f8
41 7c: 05 fe 98 25 fld.q -512\(%r12\)\+\+,%f24
51 a4: 04 60 fc 20 fld.q %r12\(%r7\),%f28
56 b8: 04 88 88 21 fld.q %r17\(%r12\),%f8
66 e0: 05 60 fc 20 fld.q %r12\(%r7\)\+\+,%f28
71 f4: 05 88 90 21 fld.q %r17\(%r12\)\+\+,%f16
|
| fldst04.d | 24 38: 06 fe 8c 2d fst.l %f12,-508\(%r12\)
41 7c: 07 fe 8e 2d fst.l %f14,-508\(%r12\)\+\+
51 a4: 02 60 f9 28 fst.l %f25,%r12\(%r7\)
56 b8: 02 88 94 29 fst.l %f20,%r17\(%r12\)
66 e0: 03 60 e7 28 fst.l %f7,%r12\(%r7\)\+\+
71 f4: 03 88 8c 29 fst.l %f12,%r17\(%r12\)\+\+
|
| fldst05.d | 24 38: 00 fe 84 2d fst.d %f4,-512\(%r12\)
41 7c: 01 fe 9c 2d fst.d %f28,-512\(%r12\)\+\+
51 a4: 00 60 f2 28 fst.d %f18,%r12\(%r7\)
56 b8: 00 88 88 29 fst.d %f8,%r17\(%r12\)
66 e0: 01 60 ee 28 fst.d %f14,%r12\(%r7\)\+\+
71 f4: 01 88 98 29 fst.d %f24,%r17\(%r12\)\+\+
|
| fldst06.d | 24 38: 04 fe 88 2d fst.q %f8,-512\(%r12\)
41 7c: 05 fe 98 2d fst.q %f24,-512\(%r12\)\+\+
51 a4: 04 60 fc 28 fst.q %f28,%r12\(%r7\)
56 b8: 04 88 88 29 fst.q %f8,%r17\(%r12\)
66 e0: 05 60 fc 28 fst.q %f28,%r12\(%r7\)\+\+
71 f4: 05 88 90 29 fst.q %f16,%r17\(%r12\)\+\+
|
| fldst07.d | 24 38: 06 fe 8c 65 pfld.l -508\(%r12\),%f12
41 7c: 07 fe 8e 65 pfld.l -508\(%r12\)\+\+,%f14
51 a4: 02 60 f9 60 pfld.l %r12\(%r7\),%f25
56 b8: 02 88 94 61 pfld.l %r17\(%r12\),%f20
66 e0: 03 60 e7 60 pfld.l %r12\(%r7\)\+\+,%f7
71 f4: 03 88 8c 61 pfld.l %r17\(%r12\)\+\+,%f12
|
| fldst08.d | 24 38: 00 fe 84 65 pfld.d -512\(%r12\),%f4
41 7c: 01 fe 9c 65 pfld.d -512\(%r12\)\+\+,%f28
51 a4: 00 60 f2 60 pfld.d %r12\(%r7\),%f18
56 b8: 00 88 88 61 pfld.d %r17\(%r12\),%f8
66 e0: 01 60 ee 60 pfld.d %r12\(%r7\)\+\+,%f14
71 f4: 01 88 98 61 pfld.d %r17\(%r12\)\+\+,%f24
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-powerpc/ |
| tlsso.d | 13 .* (e9 82 80 78|78 80 82 e9) ld r12,-32648\(r2\)
14 .* (7d 89 03 a6|a6 03 89 7d) mtctr r12
63 .* (7d 88 02 a6|a6 02 88 7d) mflr r12
67 .* (7d 88 03 a6|a6 03 88 7d) mtlr r12
69 .* (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
71 .* (7d 89 03 a6|a6 03 89 7d) mtctr r12
|
| /external/boringssl/src/crypto/bn/asm/ |
| x86_64-mont5.pl | 92 push %r12
110 mov $bp,%r12 # reassign $bp
112 $bp="%r12";
350 mov -24(%rsi),%r12
377 push %r12
438 mov -24(%rsi),%r12
454 $bp="%r12";
909 my @A1=("%r12","%r13");
928 push %r12
1009 mov -24(%rsi),%r12
[all...] |
| /external/libvpx/libvpx/vp8/common/arm/armv6/ |
| simpleloopfilter_v6.asm | 61 ldrb r12, [r2] ; blimit
66 orr r12, r12, r12, lsl #8 ; blimit
68 orr r12, r12, r12, lsl #16 ; blimit
85 usub8 r10, r12, r10 ; compare to flimit. usub8 sets GE flags
144 ldrb r12, [r2] ; r12: blimi
[all...] |
