| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.h | 104 /// from the LLVM IR Function and fixup the ISD:InputArg values before
108 const SmallVectorImpl<ISD::InputArg> &Ins,
109 SmallVectorImpl<ISD::InputArg> &OrigIns) const;
111 const SmallVectorImpl<ISD::InputArg> &Ins) const;
133 ISD::LoadExtType ExtType,
147 const SmallVectorImpl<ISD::OutputArg> &Outs,
222 // AMDIL ISD Opcodes
223 FIRST_NUMBER = ISD::BUILTIN_OP_END,
228 // End AMDIL ISD Opcodes
301 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 96 if (Addr.getOpcode() == ISD::ADD) {
137 case ISD::Constant: {
197 case ISD::BRIND:
215 if (Chain->getOpcode() != ISD::TokenFactor)
229 return CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, Ops);
237 if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
268 nextAddr->getOperand(0)->getOpcode() == ISD::TargetBlockAddress) {
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 240 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
241 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
331 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
332 Addr.getOpcode() == ISD::TargetGlobalAddress))
341 if (Addr.getOpcode() == ISD::ADD) {
370 if (Addr.getOpcode() == ISD::ADD) {
480 // * N is a ISD::BUILD_VECTOR representing a constant splat
512 // This function looks through ISD::BITCAST nodes
[all...] |
| MipsISelDAGToDAG.cpp | 208 case ISD::GLOBAL_OFFSET_TABLE:
212 case ISD::LOAD:
213 case ISD::STORE:
|
| MipsISelLowering.h | 31 // Start the numbering from where ISD NodeType finishes.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
202 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
258 /// getSetCCResultType - get the ISD::SETCC result ValueType
315 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
342 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
358 return DAG.getNode(ISD::ADD, DL, Ty,
371 return DAG.getNode(ISD::ADD, DL, Ty,
420 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl,
460 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags
[all...] |
| Mips16ISelLowering.cpp | 133 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
134 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
135 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
136 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
140 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
141 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
142 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand)
[all...] |
| MipsFastISel.cpp | 211 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
216 ISD::ArgFlagsTy ArgFlags, CCState &State) {
222 ISD::ArgFlagsTy ArgFlags, CCState &State) {
240 case ISD::AND:
243 case ISD::OR:
246 case ISD::XOR:
827 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
830 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
833 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
191 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
249 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
309 ISD::MemIndexedMode &AM,
316 SDValue &Offset, ISD::MemIndexedMode &AM,
501 ISD::ArgFlagsTy Flags) const;
513 ISD::ArgFlagsTy Flags) const;
576 const SmallVectorImpl<ISD::InputArg> &Ins,
584 const SmallVectorImpl<ISD::InputArg> &Ins,
616 const SmallVectorImpl<ISD::OutputArg> &Outs
[all...] |
| ARMSelectionDAGInfo.cpp | 95 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
97 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
214 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
223 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
238 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
245 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
| ARMCallingConv.h | 60 ISD::ArgFlagsTy &ArgFlags,
114 ISD::ArgFlagsTy &ArgFlags,
146 ISD::ArgFlagsTy &ArgFlags,
157 ISD::ArgFlagsTy &ArgFlags,
182 ISD::ArgFlagsTy &ArgFlags,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 219 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
229 ISD::CondCode CC;
775 void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
776 void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
777 void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
779 void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
780 void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
781 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
782 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
783 void visitFRem(const User &I) { visitBinary(I, ISD::FREM);
[all...] |
| InstrEmitter.cpp | 113 if (User->getOpcode() == ISD::CopyToReg &&
196 if (User->getOpcode() == ISD::CopyToReg &&
245 if (User->getOpcode() == ISD::CopyToReg &&
352 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
477 if (User->getOpcode() == ISD::CopyToReg &&
[all...] |
| SelectionDAGISel.cpp | 690 if (N->getOpcode() != ISD::CopyToReg)
[all...] |
| LegalizeTypes.cpp | [all...] |
| ScheduleDAGSDNodes.h | 69 if (Node->getOpcode() == ISD::EntryToken ||
|
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 142 static ISD::NodeType getExtendForContent(BooleanContent Content) {
146 return ISD::ANY_EXTEND;
149 return ISD::ZERO_EXTEND;
152 return ISD::SIGN_EXTEND;
184 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
185 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
595 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
638 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64CallingConvention.h | 45 MVT LocVT, ISD::ArgFlagsTy &ArgFlags,
67 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
86 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
|
| AArch64ISelLowering.h | 30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
93 // Vector bit select: similar to ISD::VSELECT but not all bits within an
180 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
191 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
269 /// Return the ISD::SETCC ValueType.
410 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
419 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
428 const SmallVectorImpl<ISD::OutputArg> &Outs,
430 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
447 const SmallVectorImpl<ISD::OutputArg> &Outs
[all...] |
| AArch64ISelDAGToDAG.cpp | 316 case ISD::SHL:
318 case ISD::SRL:
320 case ISD::SRA:
322 case ISD::ROTR:
366 if (N.getOpcode() == ISD::SIGN_EXTEND ||
367 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
369 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
383 } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
384 N.getOpcode() == ISD::ANY_EXTEND) {
395 } else if (N.getOpcode() == ISD::AND)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 46 const SmallVectorImpl<ISD::InputArg> &Ins,
52 const SmallVectorImpl<ISD::OutputArg> &Outs,
105 // AMDIL ISD Opcodes
106 FIRST_NUMBER = ISD::BUILTIN_OP_END,
114 // End AMDIL ISD Opcodes
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | 31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
504 LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
718 /// Return the value type to use for ISD::SETCC.
872 bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
[all...] |
| X86SelectionDAGInfo.cpp | 169 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
185 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
271 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
274 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
283 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.h | 25 // Start the numbering from where ISD NodeType finishes.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
59 LoadV2 = ISD::FIRST_TARGET_MEMORY_OPCODE,
480 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
487 const SmallVectorImpl<ISD::OutputArg> &,
493 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
93 // Wrappers around the ISD opcodes of the same name. The output and
288 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
434 const SmallVectorImpl<ISD::InputArg> &Ins,
442 const SmallVectorImpl<ISD::OutputArg> &Outs,
445 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/MC/ |
| MCMachOStreamer.cpp | 285 IndirectSymbolData ISD;
286 ISD.Symbol = Symbol;
287 ISD.Section = getCurrentSectionOnly();
288 getAssembler().getIndirectSymbols().push_back(ISD);
|
