| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.h | 535 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
537 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
[all...] |
| LegalizeVectorOps.cpp | 141 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
191 SDNode* Node = Op.getNode();
250 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.h | 209 SDNode *Node) const override { return 1;}
|
| AMDGPUISelLowering.cpp | 438 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
641 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
654 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
[all...] |
| SIInstrInfo.cpp | 37 static unsigned getNumOperandsNoGlue(SDNode *Node) {
44 static SDValue findChainOperand(SDNode *Load) {
52 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
[all...] |
| R600ISelLowering.cpp | 866 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 183 void ReplaceNodeResults(SDNode *N,
|
| SparcISelLowering.cpp | 627 // The caller promoted the argument, so insert an Assert?ext SDNode so we
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 392 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
395 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
402 SDNode *MultNode = MultHi.getNode();
464 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
467 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
474 SDNode *MultNode = MultHi.getNode();
528 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
548 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
663 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
783 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG
[all...] |
| MipsISelLowering.cpp | 470 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
580 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
659 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
686 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
728 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | [all...] |
| ScheduleDAG.cpp | 57 const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
314 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 450 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
|
| /external/llvm/utils/TableGen/ |
| DAGISelMatcherEmitter.cpp | 647 OS << "bool CheckNodePredicate(SDNode *Node,\n";
670 OS << "bool CheckComplexPattern(SDNode *Root, SDNode *Parent,\n";
672 OS << " SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) override {\n";
715 // FIXME: The node xform could take SDValue's instead of SDNode*'s.
720 Record *SDNode = Entry.first;
728 std::string ClassName = CGP.getSDNodeInfo(SDNode).getSDClassName();
729 if (ClassName == "SDNode")
730 OS << " SDNode *N = V.getNode();\n";
826 OS << "SDNode *SelectCode(SDNode *N) {\n"
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 237 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
662 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
722 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
770 SDNode *Node = Op.getNode();
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 739 SDNode* N = Op.getNode();
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 392 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 48 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
50 cl::desc("Enable Hexagon SDNode scheduling"));
609 /// being lowered. Returns a SDNode with the same number of values as the
[all...] |
