| /external/mesa3d/src/mesa/state_tracker/ |
| st_atom_pixeltransfer.c | 165 inst[ic].SrcReg[0].File = PROGRAM_INPUT;
166 inst[ic].SrcReg[0].Index = FRAG_ATTRIB_TEX0;
189 inst[ic].SrcReg[0].File = PROGRAM_TEMPORARY;
190 inst[ic].SrcReg[0].Index = colorTemp;
191 inst[ic].SrcReg[1].File = PROGRAM_STATE_VAR;
192 inst[ic].SrcReg[1].Index = scale_p;
193 inst[ic].SrcReg[2].File = PROGRAM_STATE_VAR;
194 inst[ic].SrcReg[2].Index = bias_p;
219 inst[ic].SrcReg[0].File = PROGRAM_TEMPORARY;
220 inst[ic].SrcReg[0].Index = colorTemp
[all...] |
| st_mesa_to_tgsi.c | 340 const struct prog_src_register *SrcReg )
342 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index );
344 if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) {
345 src = src_register( t, SrcReg->File, SrcReg->Index2 );
346 if (SrcReg->RelAddr2)
348 SrcReg->Index);
350 src = ureg_src_dimension( src, SrcReg->Index);
354 GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3
[all...] |
| /external/mesa3d/src/mesa/program/ |
| prog_execute.c | 398 inst->SrcReg[0].File == PROGRAM_INPUT &&
399 inst->SrcReg[0].Index == FRAG_ATTRIB_TEX0 + inst->TexSrcUnit) {
401 GLuint attr = inst->SrcReg[0].Index;
669 fetch_vector4(&inst->SrcReg[0], machine, a);
680 fetch_vector4(&inst->SrcReg[0], machine, a);
681 fetch_vector4(&inst->SrcReg[1], machine, b);
697 fetch_vector4ui(&inst->SrcReg[0], machine, a);
698 fetch_vector4ui(&inst->SrcReg[1], machine, b);
709 fetch_vector4(&inst->SrcReg[0], machine, t);
770 fetch_vector4(&inst->SrcReg[0], machine, a)
[all...] |
| prog_instruction.c | 46 inst[i].SrcReg[0].File = PROGRAM_UNDEFINED;
47 inst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP;
48 inst[i].SrcReg[1].File = PROGRAM_UNDEFINED;
49 inst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP;
50 inst[i].SrcReg[2].File = PROGRAM_UNDEFINED;
51 inst[i].SrcReg[2].Swizzle = SWIZZLE_NOOP;
318 if (inst->SrcReg[i].File == inst->DstReg.File &&
319 inst->SrcReg[i].Index == inst->DstReg.Index) {
325 GLuint swizzle = GET_SWZ(inst->SrcReg[i].Swizzle, chan);
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_emulate_branches.c | 79 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
81 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
82 inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index;
83 inst->U.I.SrcReg[0].Swizzle = 0;
84 inst->U.I.SrcReg[0].Abs = 0;
85 inst->U.I.SrcReg[0].Negate = 0;
169 inst_mov->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
170 inst_mov->U.I.SrcReg[0].Index = index;
188 inst_cmp->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0]
[all...] |
| r500_fragprog.c | 56 var_list, inst_if->Type, &inst_if->U.I.SrcReg[0]);
99 if (GET_SWZ(inst_if->U.I.SrcReg[0].Swizzle, 0) == RC_SWIZZLE_X) {
113 inst_mov->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0];
115 inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(
116 inst_mov->U.I.SrcReg[0].Swizzle,
120 inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(
121 inst_mov->U.I.SrcReg[0].Swizzle,
165 temp_src = writer->Inst->U.I.SrcReg[0];
166 writer->Inst->U.I.SrcReg[0]
[all...] |
| radeon_program.h | 66 struct rc_src_register SrcReg[2];
78 struct rc_src_register SrcReg[3];
|
| radeon_program_print.c | 204 rc_print_register(f, inst.SrcReg[0].File,
205 inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr);
208 rc_print_register(f, inst.SrcReg[1].File,
209 inst.SrcReg[1].Index,inst.SrcReg[1].RelAddr);
211 rc_print_register(f, inst.SrcReg[0].File,
212 inst.SrcReg[0].Index,inst.SrcReg[0].RelAddr);
215 rc_print_register(f, inst.SrcReg[1].File
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| i915_fragprog.c | 275 GLuint coord = src_vector( p, &inst->SrcReg[0], program); \
292 (N<1)?0:src_vector( p, &inst->SrcReg[0], program), \
293 (N<2)?0:src_vector( p, &inst->SrcReg[1], program), \
294 (N<3)?0:src_vector( p, &inst->SrcReg[2], program)); \
328 if (inst->SrcReg[a].File == PROGRAM_TEMPORARY) {
331 if (inst->SrcReg[a].Index >= I915_MAX_TEMPORARY)
334 regsUsed |= 1 << inst->SrcReg[a].Index;
337 const unsigned field = GET_SWZ(inst->SrcReg[a].Swizzle, c);
340 live_components[inst->SrcReg[a].Index] |= (1U << field);
414 src0 = src_vector(p, &inst->SrcReg[0], program)
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 181 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
193 SrcReg = MCI.getOperand(1).getReg();
197 if (HexagonMCInstrInfo::isIntReg(SrcReg) &&
198 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
202 if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
211 SrcReg = MCI.getOperand(1).getReg();
213 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
232 SrcReg = MCI.getOperand(1).getReg();
234 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
242 SrcReg = MCI.getOperand(1).getReg()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 81 unsigned DestReg, unsigned SrcReg,
87 if (Mips::GPR32RegClass.contains(SrcReg)) {
92 } else if (Mips::CCRRegClass.contains(SrcReg))
94 else if (Mips::FGR32RegClass.contains(SrcReg))
96 else if (Mips::HI32RegClass.contains(SrcReg)) {
98 SrcReg = 0;
99 } else if (Mips::LO32RegClass.contains(SrcReg)) {
101 SrcReg = 0;
102 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
104 else if (Mips::LO32DSPRegClass.contains(SrcReg))
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_fragshader.c | 42 const struct atifragshader_src_register srcReg,
45 const GLuint index = srcReg.Index;
46 const GLuint srcmod = srcReg.argMod;
47 const GLuint srcrep = srcReg.argRep;
170 inst->SrcReg[optype][0], 1, &tfactor);
172 inst->SrcReg[optype][1], 2, &tfactor);
180 inst->SrcReg[optype][0], 2, &tfactor);
185 inst->SrcReg[optype][2], 2, &tfactor);
189 inst->SrcReg[optype][0], 0, &tfactor);
191 inst->SrcReg[optype][1], 1, &tfactor)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.h | 35 unsigned DestReg, unsigned SrcReg,
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 282 unsigned DestReg, unsigned SrcReg,
296 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
298 .addReg(SrcReg, getKillRegState(KillSrc));
299 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {
304 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
306 .addReg(SrcReg, getKillRegState(KillSrc));
307 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
310 .addReg(SrcReg, getKillRegState(KillSrc));
317 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
321 .addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| SparcInstrInfo.h | 81 unsigned DestReg, unsigned SrcReg,
86 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.h | 44 unsigned DestReg, unsigned SrcReg,
49 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 57 unsigned DestReg, unsigned SrcReg,
62 unsigned SrcReg, bool isKill,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 66 unsigned DestReg, unsigned SrcReg,
71 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_program.c | 196 if (prog->Instructions[i].SrcReg[r].RelAddr &&
197 prog->Instructions[i].SrcReg[r].File == PROGRAM_INPUT) {
214 (prog->Instructions[i].SrcReg[0].RelAddr &&
215 prog->Instructions[i].SrcReg[0].File == PROGRAM_TEMPORARY) ||
216 (prog->Instructions[i].SrcReg[1].RelAddr &&
217 prog->Instructions[i].SrcReg[1].File == PROGRAM_TEMPORARY) ||
218 (prog->Instructions[i].SrcReg[2].RelAddr &&
219 prog->Instructions[i].SrcReg[2].File == PROGRAM_TEMPORARY)) {
|
| /external/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 36 unsigned DestReg, unsigned SrcReg,
38 if (BPF::GPRRegClass.contains(DestReg, SrcReg))
40 .addReg(SrcReg, getKillRegState(KillSrc));
47 unsigned SrcReg, bool IsKill, int FI,
56 .addReg(SrcReg, getKillRegState(IsKill))
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCMIPeephole.cpp | 59 // Find the "true" register represented by SrcReg (following chains
61 unsigned lookThruCopyLike(unsigned SrcReg);
193 // the original SrcReg unless it is the target of a copy-like
197 unsigned PPCMIPeephole::lookThruCopyLike(unsigned SrcReg) {
201 MachineInstr *MI = MRI->getVRegDef(SrcReg);
203 return SrcReg;
216 SrcReg = CopySrcReg;
|
| /external/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 239 void addSource(unsigned SrcReg, unsigned SrcSubReg) {
240 RegSrcs.push_back(TargetInstrInfo::RegSubRegPair(SrcReg, SrcSubReg));
243 void setSource(int Idx, unsigned SrcReg, unsigned SrcSubReg) {
245 RegSrcs[Idx] = TargetInstrInfo::RegSubRegPair(SrcReg, SrcSubReg);
415 unsigned SrcReg, DstReg, SubIdx;
416 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
420 TargetRegisterInfo::isPhysicalRegister(SrcReg))
423 if (MRI->hasOneNonDBGUse(SrcReg))
434 // The ext instr may be operating on a sub-register of SrcReg as well.
437 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses o
[all...] |
| PHIElimination.cpp | 361 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
364 isImplicitlyDefined(SrcReg, MRI);
365 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
381 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
395 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
401 .addReg(SrcReg, 0, SrcSubReg);
405 // We only need to update the LiveVariables kill of SrcReg if this was the
406 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
409 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
410 !LV->isLiveOut(SrcReg, opBlock))
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 52 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
113 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
117 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
121 MachineBasicBlock::iterator MBBI, unsigned SrcReg,
155 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
157 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
162 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
198 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
203 DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
|
| AArch64InstrInfo.cpp | 439 unsigned SrcReg = Cond[2].getReg();
442 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
444 .addReg(SrcReg)
448 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
450 .addReg(SrcReg)
595 unsigned &SrcReg, unsigned &DstReg,
607 SrcReg = MI.getOperand(1).getReg();
649 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
651 bool AArch64InstrInfo::analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
670 SrcReg = MI->getOperand(1).getReg()
[all...] |
