| /external/mesa3d/src/mesa/program/ |
| program.c | 680 if (inst[i].SrcReg[j].File == oldFile &&
681 inst[i].SrcReg[j].Index == oldIndex) {
682 inst[i].SrcReg[j].File = newFile;
683 inst[i].SrcReg[j].Index = newIndex;
707 GLuint f = inst[i].SrcReg[j].File;
711 inst[i].SrcReg[j].Index += offset;
878 if (inst->SrcReg[j].File == file) {
879 ASSERT(inst->SrcReg[j].Index < usedSize);
880 if(inst->SrcReg[j].Index < usedSize)
881 used[inst->SrcReg[j].Index] = GL_TRUE
[all...] |
| program_parser.h | 127 struct asm_src_register SrcReg[3];
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 682 unsigned SrcReg, bool KillSrc,
695 MIB.addReg(SrcReg, getKillRegState(KillSrc));
704 unsigned DestReg, unsigned SrcReg,
707 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
711 .addReg(SrcReg, getKillRegState(KillSrc))));
716 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
725 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
727 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
732 MIB.addReg(SrcReg, getKillRegState(KillSrc));
734 MIB.addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| ARMFastISel.cpp | 174 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
181 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
185 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
186 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
443 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
449 .addReg(SrcReg));
453 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
459 .addReg(SrcReg));
[all...] |
| ARMBaseInstrInfo.h | 171 unsigned SrcReg, bool KillSrc,
178 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
183 unsigned SrcReg, bool isKill, int FrameIndex,
252 /// in SrcReg and SrcReg2 if having two register operands, and the value it
255 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
263 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
|
| ARMAsmPrinter.cpp | [all...] |
| Thumb2InstrInfo.cpp | 114 unsigned DestReg, unsigned SrcReg,
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
121 .addReg(SrcReg, getKillRegState(KillSrc)));
126 unsigned SrcReg, bool isKill, int FI,
142 .addReg(SrcReg, getKillRegState(isKill))
152 MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
155 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
156 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
162 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 334 unsigned DestReg, unsigned SrcReg,
337 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg);
341 .addReg(SrcReg, getKillRegState(KillSrc))
346 if (GRDest && SrcReg == XCore::SP) {
353 .addReg(SrcReg, getKillRegState(KillSrc));
361 unsigned SrcReg, bool isKill,
376 .addReg(SrcReg, getKillRegState(isKill))
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 187 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
189 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
190 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 87 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
89 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
94 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
120 } else if (DestReg != SrcReg)
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
172 VRBase = SrcReg;
177 VRBase).addReg(SrcReg);
497 unsigned SrcReg, DstReg, DefSubIdx;
499 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
501 TRC == MRI->getRegClass(SrcReg)) {
[all...] |
| FunctionLoweringInfo.cpp | 442 unsigned SrcReg = ValueMap[V];
443 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
447 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
479 unsigned SrcReg = ValueMap[V];
480 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
484 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
|
| /external/llvm/lib/CodeGen/ |
| TwoAddressInstructionPass.cpp | 380 unsigned &SrcReg, unsigned &DstReg,
382 SrcReg = 0;
386 SrcReg = MI.getOperand(1).getReg();
389 SrcReg = MI.getOperand(2).getReg();
393 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
464 unsigned SrcReg, DstReg;
467 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
469 Reg = SrcReg;
503 unsigned SrcReg;
505 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
[all...] |
| RegisterCoalescer.cpp | 143 /// Attempt to join intervals corresponding to SrcReg/DstReg, which are the
200 /// Replace all defs and uses of SrcReg to DstReg and update the subregister
204 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
304 SrcReg = DstReg = 0;
356 // SrcReg will be merged with a sub-register of DstReg.
360 // DstReg will be merged with a sub-register of SrcReg.
372 // Prefer SrcReg to be a sub-register of DstReg.
386 SrcReg = Src;
394 std::swap(SrcReg, DstReg);
407 // Find the virtual register that is SrcReg
[all...] |
| MachineSink.cpp | 162 unsigned SrcReg = MI->getOperand(1).getReg();
164 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
166 !MRI->hasOneNonDBGUse(SrcReg))
169 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
174 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
179 MRI->replaceRegWith(DstReg, SrcReg);
184 MRI->clearKillFlags(SrcReg);
|
| TailDuplication.cpp | 263 unsigned SrcReg = LI->second[j].second;
264 SSAUpdate.AddAvailableValue(SrcBB, SrcReg);
372 unsigned SrcReg = MI.getOperand(i).getReg();
373 UsedByPhi->insert(SrcReg);
402 unsigned SrcReg = MI->getOperand(SrcOpIdx).getReg();
404 LocalVRMap.insert(std::make_pair(DefReg, SrcReg));
409 Copies.push_back(std::make_pair(NewDef, SrcReg));
516 unsigned SrcReg = LI->second[j].second;
518 II->getOperand(Idx).setReg(SrcReg);
522 MIB.addReg(SrcReg).addMBB(SrcBB)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 197 unsigned &SrcReg, unsigned &DstReg,
334 unsigned DestReg, unsigned SrcReg,
338 unsigned SrcReg, bool isKill, int FrameIndex,
342 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
502 /// in SrcReg and SrcReg2 if having two register operands, and the value it
505 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
512 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| r3xx_fragprog.c | 76 inst->SrcReg[i] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[i]);
|
| radeon_dataflow.c | 199 if (inst->U.I.SrcReg[src].File == RC_FILE_NONE)
202 if (inst->U.I.SrcReg[src].File == RC_FILE_PRESUB) {
207 cb(userdata, inst, &inst->U.I.PreSub.SrcReg[i]);
210 cb(userdata, inst, &inst->U.I.SrcReg[src]);
358 rc_register_file file = inst->SrcReg[src].File;
359 unsigned int index = inst->SrcReg[src].Index;
372 file = inst->PreSub.SrcReg[i].File;
373 index = inst->PreSub.SrcReg[i].Index;
375 inst->PreSub.SrcReg[i].File = file;
376 inst->PreSub.SrcReg[i].Index = index
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 37 unsigned &SrcReg, unsigned &DstReg,
124 unsigned SrcReg, bool isKill,
|
| R600InstrInfo.cpp | 51 unsigned DestReg, unsigned SrcReg,
55 && AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex))
69 && !AMDGPU::R600_Reg128RegClass.contains(SrcReg));
72 .addReg(SrcReg, getKillRegState(KillSrc))
|
| /external/llvm/lib/Target/Mips/ |
| MipsOptimizePICCall.cpp | 134 unsigned SrcReg = I->getOperand(0).getReg();
135 unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64;
137 .addReg(SrcReg);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 186 unsigned SrcReg = MI.getOperand(2).getReg();
187 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
188 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 243 // STriw_pred [R30], ofst, SrcReg;
249 int SrcReg = MI->getOperand(2).getReg();
250 assert(Hexagon::PredRegsRegClass.contains(SrcReg) &&
261 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
270 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
279 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
|
| HexagonInstrInfo.h | 146 unsigned DestReg, unsigned SrcReg,
155 unsigned SrcReg, bool isKill, int FrameIndex,
227 /// in SrcReg and SrcReg2 if having two register operands, and the value it
231 unsigned &SrcReg, unsigned &SrcReg2,
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCompound.cpp | 84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
115 SrcReg = MI.getOperand(1).getReg();
117 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
127 SrcReg = MI.getOperand(1).getReg();
129 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg))
|
