| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-aarch64/ |
| local-addend-r.d | 3 #ld: -e0 -r
|
| tls-relax-gdesc-ie-2.d | 2 #ld: -T relocs.ld -e0
|
| tls-relax-gdesc-le-2.d | 2 #ld: -T relocs.ld -e0
|
| tls-relax-ie-le-2.d | 2 #ld: -T relocs.ld -e0
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-arm/ |
| emit-relocs1.d | 2 #ld: -Ttext 0x10000 --defsym target=0xc000 -e0 --emit-relocs
|
| tls-app.d | 16 81e0: 00000004 .word 0x00000004
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/ |
| mips16-and-micromips.d | 4 #ld: -e0
|
| eh-frame1-n32.d | 132 00000150 00000010 00000154 FDE cie=00000000 pc=000201d0..000201e0
138 00000164 00000010 00000168 FDE cie=00000000 pc=000201e0..000201f0
163 000001c8 00000010 00000154 FDE cie=00000078 pc=000202d0..000202e0
168 000001dc 00000010 00000168 FDE cie=00000078 pc=000202e0..00020300
169 DW_CFA_advance_loc: 0 to 000202e0
170 DW_CFA_advance_loc: 0 to 000202e0
171 DW_CFA_advance_loc: 0 to 000202e0
|
| eh-frame1-n64.d | 124 0+00e0 0+001c 0+002c FDE cie=0+00b8 pc=0+0200f0..0+020100
203 0+01e0 0+001c 0+0064 FDE cie=0+0180 pc=0+020190..0+0201d0
212 0+0200 0+001c 0+0204 FDE cie=0+0000 pc=0+0201d0..0+0201e0
222 0+0220 0+001c 0+0224 FDE cie=0+0000 pc=0+0201e0..0+0201f0
267 0+02c0 0+001c 0+020c FDE cie=0+00b8 pc=0+0202d0..0+0202e0
276 0+02e0 0+001c 0+022c FDE cie=0+00b8 pc=0+0202e0..0+020300
277 DW_CFA_advance_loc: 0 to 0+0202e0
278 DW_CFA_advance_loc: 0 to 0+0202e0
279 DW_CFA_advance_loc: 0 to 0+0202e0
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mmix/ |
| bpo-4m.d | 21 07e0 00000000 00000032 00000000 00000133 .*
|
| bpo-6m.d | 26 07e0 00000000 0000dc00 00000000 0000dd00 .*
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-powerpc/ |
| tocopt.d | 8 100000e0 (e8c50000|0000c5e8) (3fa00000|0000a03f) (3bbd8010|1080bd3b) (7c62e82a|2ae8627c) .*
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/ |
| fldst03.d | 18 20: f4 7f e0 24 fld.q 32752\(%r7\),%f0
21 2c: 04 e0 34 25 fld.q -8192\(%r9\),%f20
35 64: f5 7f e0 24 fld.q 32752\(%r7\)\+\+,%f0
38 70: 05 e0 2c 25 fld.q -8192\(%r9\)\+\+,%f12
57 bc: 04 e0 a4 21 fld.q %r28\(%r13\),%f4
66 e0: 05 60 fc 20 fld.q %r12\(%r7\)\+\+,%f28
72 f8: 05 e0 b4 21 fld.q %r28\(%r13\)\+\+,%f20
|
| fldst06.d | 18 20: f4 7f e0 2c fst.q %f0,32752\(%r7\)
21 2c: 04 e0 34 2d fst.q %f20,-8192\(%r9\)
35 64: f5 7f e0 2c fst.q %f0,32752\(%r7\)\+\+
38 70: 05 e0 2c 2d fst.q %f12,-8192\(%r9\)\+\+
57 bc: 04 e0 a4 29 fst.q %f4,%r28\(%r13\)
66 e0: 05 60 fc 28 fst.q %f28,%r12\(%r7\)\+\+
72 f8: 05 e0 b4 29 fst.q %f20,%r28\(%r13\)\+\+
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/ |
| simpshft.d | 10 0: (e0 0f 64 78|78 64 0f e0) rldicl r4,r3,1,63
39 74: (e0 0f 64 78|78 64 0f e0) rldicl r4,r3,1,63
42 80: (e0 07 64 78|78 64 07 e0) clrldi r4,r3,63
66 e0: (3e 00 64 54|54 64 00 3e) rotlwi r4,r3,0
|
| altivec.d | 21 2c: (7e e0 40 8e|8e 40 e0 7e) lvewx v23,0,r8
30 50: (7f e0 42 a6|a6 42 e0 7f) mfvrsave r31
37 6c: (7e e0 a1 4e|4e a1 e0 7e) stvehx v23,0,r20
39 74: (7f e0 09 8e|8e 09 e0 7f) stvewx v31,0,r1
49 9c: (12 0e e0 00|00 e0 0e 12) vaddubm v16,v14,v2
[all...] |
| /external/opencv3/samples/cpp/ |
| delaunay2.cpp | 56 int e0=0, vertex=0; local
58 subdiv.locate(fp, e0, vertex);
60 if( e0 > 0 )
62 int e = e0;
71 while( e != e0 );
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
| flow2.d | 56 6a: e0 1b IF CC JUMP 0x2a <MY_LABEL1>;
85 ac: 82 e0 02 00 LSETUP\(0xb0 <MY_LABEL1\+0x86>, 0xb0 <MY_LABEL1\+0x86>\) LC0;
86 b0: 84 e0 06 00 LSETUP\(0xb8 <beg_poll_bit>, 0xbc <end_poll_bit>\) LC0;
95 c0: 92 e0 03 00 LSETUP\(0xc4 <end_poll_bit\+0x8>, 0xc6 <end_poll_bit\+0xa>\) LC1;
96 c4: 93 e0 05 00 LSETUP\(0xca <FIR_filter>, 0xce <bottom_of_FIR_filter>\) LC1;
104 d2: a2 e0 04 10 LSETUP\(0xd6 <bottom_of_FIR_filter\+0x8>, 0xda <bottom_of_FIR_filter\+0xc>\) LC0 = P1;
105 d6: e2 e0 04 10 LSETUP\(0xda <bottom_of_FIR_filter\+0xc>, 0xde <bottom_of_FIR_filter\+0x10>\) LC0 = P1 >> 0x1;
106 da: 82 e0 03 00 LSETUP\(0xde <bottom_of_FIR_filter\+0x10>, 0xe0 <bottom_of_FIR_filter\+0x12>\) LC0;
108 e0: 11 60 R1 = 0x2 \(X\);.*
109 e2: 90 e0 00 00 LSETUP\(0xe2 <bottom_of_FIR_filter\+0x14>, 0xe2 <bottom_of_FIR_filter\+0x14>\) LC1
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| x86-64-bmi-intel.d | 35 [ ]*[a-f0-9]+: c4 e2 e0 f2 f0 andn rsi,rbx,rax
36 [ ]*[a-f0-9]+: c4 e2 e0 f2 31 andn rsi,rbx,QWORD PTR \[rcx\]
47 [ ]*[a-f0-9]+: c4 e2 e0 f3 d8 blsi rbx,rax
48 [ ]*[a-f0-9]+: c4 e2 e0 f3 19 blsi rbx,QWORD PTR \[rcx\]
51 [ ]*[a-f0-9]+: c4 e2 e0 f3 d0 blsmsk rbx,rax
52 [ ]*[a-f0-9]+: c4 e2 e0 f3 11 blsmsk rbx,QWORD PTR \[rcx\]
55 [ ]*[a-f0-9]+: c4 e2 e0 f3 c8 blsr rbx,rax
56 [ ]*[a-f0-9]+: c4 e2 e0 f3 09 blsr rbx,QWORD PTR \[rcx\]
89 [ ]*[a-f0-9]+: c4 e2 e0 f2 f0 andn rsi,rbx,rax
90 [ ]*[a-f0-9]+: c4 e2 e0 f2 31 andn rsi,rbx,QWORD PTR \[rcx\
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/or1k/ |
| allinsn.d | 93 e0: 21 00 80 00 l\.trap 0x8000
118 124: 1b e0 ff ff l\.movhi r31,0xffff
120 12c: 19 e0 7f ff l\.movhi r15,0x7fff
123 138: 1a e0 e8 ac l\.movhi r23,0xe8ac
176 000001e0 <l_lbs>:
177 1e0: 90 00 00 00 l\.lbs r0,0\(r0\)
237 2a0: e0 00 00 08 l\.sll r0,r0,r0
241 2b0: e0 21 08 08 l\.sll r1,r1,r1
256 000002e0 <l_srl>:
257 2e0: e0 00 00 48 l\.srl r0,r0,r
[all...] |
| /external/fio/crc/ |
| sha512.c | 70 #define e0(x) (RORuint64_t(x,28) ^ RORuint64_t(x,34) ^ RORuint64_t(x,39)) macro
125 t2 = e0(a) + Maj(a,b,c); d+=t1; h=t1+t2;
127 t2 = e0(h) + Maj(h,a,b); c+=t1; g=t1+t2;
129 t2 = e0(g) + Maj(g,h,a); b+=t1; f=t1+t2;
131 t2 = e0(f) + Maj(f,g,h); a+=t1; e=t1+t2;
133 t2 = e0(e) + Maj(e,f,g); h+=t1; d=t1+t2;
135 t2 = e0(d) + Maj(d,e,f); g+=t1; c=t1+t2;
137 t2 = e0(c) + Maj(c,d,e); f+=t1; b=t1+t2;
139 t2 = e0(b) + Maj(b,c,d); e+=t1; a=t1+t2;
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arc/ |
| add.d | 15 18: 00 84 e0 47 47e08400 add 0,r1,r2
18 24: 00 84 e0 47 47e08400 add 0,r1,r2
21 30: 00 84 e0 47 47e08400 add 0,r1,r2
24 3c: 00 84 e0 47 47e08400 add 0,r1,r2
66 e0: 05 00 00 00
70 f0: 00 85 e0 47 47e08500 add.f 0,r1,r2
|
| and.d | 15 18: 00 84 e0 67 67e08400 and 0,r1,r2
18 24: 00 84 e0 67 67e08400 and 0,r1,r2
21 30: 00 84 e0 67 67e08400 and 0,r1,r2
24 3c: 00 84 e0 67 67e08400 and 0,r1,r2
66 e0: 05 00 00 00
70 f0: 00 85 e0 67 67e08500 and.f 0,r1,r2
|
| bic.d | 15 18: 00 84 e0 77 77e08400 bic 0,r1,r2
18 24: 00 84 e0 77 77e08400 bic 0,r1,r2
21 30: 00 84 e0 77 77e08400 bic 0,r1,r2
24 3c: 00 84 e0 77 77e08400 bic 0,r1,r2
66 e0: 05 00 00 00
70 f0: 00 85 e0 77 77e08500 bic.f 0,r1,r2
|
| sub.d | 15 18: 00 84 e0 57 57e08400 sub 0,r1,r2
18 24: 00 84 e0 57 57e08400 sub 0,r1,r2
21 30: 00 84 e0 57 57e08400 sub 0,r1,r2
24 3c: 00 84 e0 57 57e08400 sub 0,r1,r2
66 e0: 05 00 00 00
70 f0: 00 85 e0 57 57e08500 sub.f 0,r1,r2
|
