| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips5-wrong-error.s | 21 c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
38 mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| valid.s | 7 abs.s $f9,$f16
28 c.ngle.d $f0,$f16
56 lwc1 $f16,10225($k0)
73 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips5-wrong-error.s | 21 c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
38 mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips5-wrong-error.s | 21 c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
38 mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips5-wrong-error.s | 21 c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
38 mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| valid.s | 7 abs.s $f9,$f16
45 c.ngle.d $f0,$f16
54 cvt.d.l $f4,$f16
139 lwc1 $f16,10225($k0)
170 msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
175 mul.d $f20,$f20,$f16
187 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips5-wrong-error.s | 24 c.olt.ps $fcc3,$f7,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
40 mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/v8/test/webkit/ |
| toString-elision-trailing-comma.js | 89 function f16() { function
131 testToStringAndLength("f16", 3);
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/ |
| mips16-intermix-1.s | 87 jal f16
|
| /external/libjpeg-turbo/simd/ |
| jsimd_mips_dspr2_asm.h | 75 #define f16 $f16 macro
|
| /external/llvm/test/MC/ARM/ |
| directive-arch_extension-fp.s | 48 vcvtb.f64.f16 d0, s0
50 vcvtb.f16.f64 s0, d0
52 vcvtt.f64.f16 d0, s0
54 vcvtt.f16.f64 s0, d0
184 vcvtb.f64.f16 d0, s0
186 vcvtb.f16.f64 s0, d0
188 vcvtt.f64.f16 d0, s0
190 vcvtt.f16.f64 s0, d0
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 18 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| valid.s | 7 abs.s $f9,$f16
45 c.ngle.d $f0,$f16
56 cvt.d.l $f4,$f16
147 lwc1 $f16,10225($k0)
185 msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
192 mul.d $f20,$f20,$f16
204 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
|
| /external/valgrind/none/tests/mips32/ |
| MoveIns.c | 299 TESTINSNMOVE("mfc1 $s7, $f16", 64, f16, s7);
328 TESTINSNMOVEt("mtc1 $s7, $f16", 64, f16, s7);
357 TESTINSNMOVE1s("mov.s $f15, $f16", 64, f15, f16);
358 TESTINSNMOVE1s("mov.s $f16, $f17", 0, f16, f17);
385 TESTINSNMOVE1d("mov.d $f14, $f16", 48, f14, f16);
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/ |
| float02.d | 18 20: b3 38 10 48 famov.sd %f7,%f16
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 7 abs.s $f9,$f16
45 c.ngle.d $f0,$f16
95 lwc1 $f16,10225($k0)
130 msub.s $f12,$f19,$f10,$f16
134 mthc1 $zero,$f16
139 mul.d $f20,$f20,$f16
151 nmsub.d $f30,$f8,$f16,$f30
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 7 abs.s $f9,$f16
45 c.ngle.d $f0,$f16
95 lwc1 $f16,10225($k0)
130 msub.s $f12,$f19,$f10,$f16
134 mthc1 $zero,$f16
139 mul.d $f20,$f20,$f16
151 nmsub.d $f30,$f8,$f16,$f30
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 7 abs.s $f9,$f16
45 c.ngle.d $f0,$f16
96 lwc1 $f16,10225($k0)
131 msub.s $f12,$f19,$f10,$f16
135 mthc1 $zero,$f16
140 mul.d $f20,$f20,$f16
152 nmsub.d $f30,$f8,$f16,$f30
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 7 abs.s $f9,$f16
45 c.ngle.d $f0,$f16
54 cvt.d.l $f4,$f16
140 lwc1 $f16,10225($k0)
171 msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28]
176 mul.d $f20,$f20,$f16
188 nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 7 abs.s $f9,$f16
45 c.ngle.d $f0,$f16
56 cvt.d.l $f4,$f16
163 lwc1 $f16,10225($k0)
199 msub.s $f12,$f19,$f10,$f16
203 mthc1 $zero,$f16
208 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 7 abs.s $f9,$f16
45 c.ngle.d $f0,$f16
56 cvt.d.l $f4,$f16
163 lwc1 $f16,10225($k0)
199 msub.s $f12,$f19,$f10,$f16
203 mthc1 $zero,$f16
208 mul.d $f20,$f20,$f16
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 7 abs.s $f9,$f16
45 c.ngle.d $f0,$f16
56 cvt.d.l $f4,$f16
164 lwc1 $f16,10225($k0)
200 msub.s $f12,$f19,$f10,$f16
204 mthc1 $zero,$f16
209 mul.d $f20,$f20,$f16
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 130 case MVT::f16: return "f16";
211 case MVT::f16: return Type::getHalfTy(Context);
285 case Type::HalfTyID: return MVT(MVT::f16);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64CallingConvention.h | 92 else if (LocVT.SimpleTy == MVT::f16)
|
| /external/llvm/test/MC/AArch64/ |
| ldr-pseudo.s | 167 // CHECK-LABEL: f16:
168 f16: label
|
