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  /external/iputils/
rarpd.c 333 static struct sock_filter insns[] = { local
340 sizeof insns / sizeof(insns[0]),
341 insns
ping.c 1375 static struct sock_filter insns[] = { local
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  /external/owasp/sanitizer/tools/findbugs/lib/
asm-analysis-3.3.jar 
  /prebuilts/tools/common/m2/repository/asm/asm-analysis/3.3.1/
asm-analysis-3.3.1.jar 
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
x86-64-specific-reg.s 1 # 64bit insns with special register requirements
bmi.d 3 #name: i386 BMI insns
general.l 79 32 # test various segment reg insns
x86-64-fxsave-intel.d 2 #name: x86-64 fxsave/fxrstor insns (Intel disassembly)
x86-64-fxsave.d 2 #name: x86-64 fxsave/fxrstor insns
bmi-intel.d 3 #name: i386 BMI insns (Intel disassembly)
bmi2-intel.d 3 #name: i386 BMI2 insns (Intel disassembly)
bmi2.d 3 #name: i386 BMI2 insns
x86-64-avx512dq-rcigrd-intel.d 3 #name: x86_64 AVX512DQ rcig insns (Intel disassembly)
x86-64-avx512dq-rcigrd.d 3 #name: x86_64 AVX512DQ rcig insns
x86-64-avx512dq-rcigrne-intel.d 3 #name: x86_64 AVX512DQ rcig insns (Intel disassembly)
x86-64-avx512dq-rcigrne.d 3 #name: x86_64 AVX512DQ rcig insns
x86-64-avx512dq-rcigru-intel.d 3 #name: x86_64 AVX512DQ rcig insns (Intel disassembly)
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68hc11/
insns.d 3 #name: insns
  /dalvik/dx/src/com/android/dx/ssa/
EscapeAnalysis.java 805 List<SsaInsn> insns = insn.getBlock().getInsns(); local
837 List<SsaInsn> insns = insn.getBlock().getInsns(); local
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  /external/dexmaker/src/dx/java/com/android/dx/ssa/
EscapeAnalysis.java 806 List<SsaInsn> insns = insn.getBlock().getInsns(); local
838 List<SsaInsn> insns = insn.getBlock().getInsns(); local
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  /art/runtime/
utils.cc 1491 const uint16_t* insns = code_item->insns_ + dex_pc; local
1666 const uint16_t* insns = code_item->insns_ + dex_pc; local
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  /external/mesa3d/src/gallium/drivers/nvc0/codegen/
nv50_ir_lowering_nvc0.cpp 283 ArrayList insns; local
285 fn->orderInstructions(insns);
288 bbFirstTex.resize(fn->allBBlocks.getSize(), insns.getSize());
289 bbFirstUse.resize(fn->allBBlocks.getSize(), insns.getSize());
299 for (int i = 0; i < insns.getSize(); ++i) {
300 Instruction *tex = reinterpret_cast<Instruction *>(insns.get(i));
308 insns.clear();
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  /external/mesa3d/src/gallium/state_trackers/d3d1x/gd3d1x/
sm4_to_tgsi.cpp 250 insn = program.insns[insn_num];
388 if(in_sub || insn_num != (program.insns.size() - 1))
417 if(program.insns[linked]->opcode == SM4_OPCODE_ENDIF)
647 sm4_to_tgsi_insn_num.resize(program.insns.size());
791 translate_insns(0, program.insns.size());
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/sh64/
basic-1.s 1 ! Various straightforward insn tests, one per insns basic insn format.
2 ! No insns with strange relocs. The insns are from the alphabetical list
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/all/
test-gen.c 128 /* This is the struct whose arrays define insns. Each func in the
138 /* Use this to group insns under a name. */
142 func ** insns; member in struct:__anon75702
618 /* Given a NULL-terminated array of insns-definitions (pointers to
619 arrays of funcs), output test code for the insns to as_in (assembly
730 /* For each group, output an asm label and the insns of the group. */
740 output_insns (group->insns, as_in, dis_out);

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