| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips64.s | 8 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 daddi $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 dadd $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 dadd $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 dmult $s7,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips5.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips4.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
10 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/test/MC/ARM/ |
| v8_IT_manual.s | 11 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
14 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
18 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
30 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
34 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
42 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
46 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
50 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
59 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
71 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT bloc
[all...] |
| not-armv4.s | 4 @ CHECK: error: instruction requires: armv5t
7 @ CHECK: error: instruction requires: armv6t2
|
| obsolete-v8.s | 4 @ CHECK: instruction requires: armv7 or earlier
7 @ CHECK: instruction requires: armv7 or earlier
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 8 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips2.s | 8 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 bnel $gp,$s4,5107 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 bgtzl $10,-3738 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 blezl $6,2974 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips5-wrong-error.s | 8 bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
9 bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 bc1any4f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 bc1any4t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 8 dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips2.s | 8 bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 bgtzl $10,-3738 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 blezl $6,2974 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 bltzall $6,488 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/llvm/test/MC/Mips/ |
| mips-expansions-bad.s | 10 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
12 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
14 # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
17 # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
18 # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
20 # 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
21 # 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
24 # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
25 # 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
27 # 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r
[all...] |
| /art/runtime/interpreter/mterp/mips64/ |
| fcvtFooter.S | 3 * from or to a floating-point type and jumps to the next instruction.
18 GOTO_OPCODE v0 # jump to next instruction
|
| /external/llvm/test/MC/X86/ |
| validate-inst-att.s | 5 # CHECK: error: invalid operand for instruction
10 # CHECK: error: invalid operand for instruction
15 # CHECK: error: invalid operand for instruction
20 # CHECK: error: invalid operand for instruction
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/iface/instruction/formats/ |
| ArrayPayload.java | 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.PayloadInstruction;
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/immutable/instruction/ |
| ImmutableInstruction20bc.java | 32 package org.jf.dexlib2.immutable.instruction;
37 import org.jf.dexlib2.iface.instruction.formats.Instruction20bc;
59 public static ImmutableInstruction20bc of(Instruction20bc instruction) {
60 if (instruction instanceof ImmutableInstruction20bc) {
61 return (ImmutableInstruction20bc)instruction;
64 instruction.getOpcode(),
65 instruction.getVerificationError(),
66 instruction.getReference());
|
| ImmutableInstruction21c.java | 32 package org.jf.dexlib2.immutable.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction21c;
58 public static ImmutableInstruction21c of(Instruction21c instruction) {
59 if (instruction instanceof ImmutableInstruction21c) {
60 return (ImmutableInstruction21c)instruction;
63 instruction.getOpcode(),
64 instruction.getRegisterA(),
65 instruction.getReference());
|
| ImmutableInstruction21ih.java | 32 package org.jf.dexlib2.immutable.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction21ih;
55 public static ImmutableInstruction21ih of(Instruction21ih instruction) {
56 if (instruction instanceof ImmutableInstruction21ih) {
57 return (ImmutableInstruction21ih)instruction;
60 instruction.getOpcode(),
61 instruction.getRegisterA(),
62 instruction.getNarrowLiteral());
|
| ImmutableInstruction31c.java | 32 package org.jf.dexlib2.immutable.instruction;
36 import org.jf.dexlib2.iface.instruction.formats.Instruction31c;
58 public static ImmutableInstruction31c of(Instruction31c instruction) {
59 if (instruction instanceof ImmutableInstruction31c) {
60 return (ImmutableInstruction31c)instruction;
63 instruction.getOpcode(),
64 instruction.getRegisterA(),
65 instruction.getReference());
|
| /ndk/tests/build/issue21132-__ARM_ARCH__/jni/ |
| Application.mk | 1 # Only armeabi-v7a* and x86 instruction for fast __swap32md
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| arm-it-bad-3.l | 2 [^:]*:4: Error: thumb conditional instruction should be in IT block -- `moveq r1,r8'
3 [^:]*:5: Error: thumb conditional instruction should be in IT block -- `movne r1,r9'
|
| insn-error-t.l | 2 [^:]*:4: Error: thumb conditional instruction should be in IT block -- `movne r1,r9'
|
| srs-arm.d | 1 # name: SRS instruction in ARM mode
|
| srs-t2.d | 1 # name: SRS instruction in Thumb-2 mode
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d30v/ |
| warn_oddreg.l | 2 .*:5: Warning: Odd numbered register used as target of multi-register instruction
3 .*:6: Warning: Odd numbered register used as target of multi-register instruction
4 .*:7: Warning: Odd numbered register used as target of multi-register instruction
5 .*:8: Warning: Odd numbered register used as target of multi-register instruction
6 .*:9: Warning: Odd numbered register used as target of multi-register instruction
7 .*:10: Warning: Odd numbered register used as target of multi-register instruction
8 .*:11: Warning: Odd numbered register used as target of multi-register instruction
9 .*:12: Warning: Odd numbered register used as target of multi-register instruction
18 .* Warning: Odd numbered register used as target of multi-register instruction
21 .* Warning: Odd numbered register used as target of multi-register instruction
[all...] |
