| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| omxVCM4P10_FilterDeblockingLuma_HorEdge_I_s.s | 131 t7 RN 7 label
237 MOV t7,#0
243 SEL t1, t7, filt ;// aqflg = filt && (aq<beta)
297 SEL aqflg, t7, filt ;// aqflg = filt && (aq<beta)
|
| omxVCM4P10_FilterDeblockingLuma_VerEdge_I_s.s | 157 t7 RN 7 label
334 MOV t7,#0
341 SEL t1, t7, filt ;// aqflg = filt && (aq<beta)
469 SEL aqflg, t7, filt ;// aqflg = filt && (aq<beta)
|
| /external/valgrind/VEX/priv/ |
| guest_mips_toIR.c | 2720 IRTemp t0, t1 = 0, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, local
12032 IRTemp t0, t1 = 0, t2, t3, t4, t5, t6, t7; local
[all...] |
| /external/opencv3/modules/core/include/opencv2/core/cuda/ |
| reduce.hpp | 178 template <typename T0, typename T1, typename T2, typename T3, typename T4, typename T5, typename T6, typename T7>
180 thrust::tuple<volatile T0*, volatile T1*, volatile T2*, volatile T3*, volatile T4*, volatile T5*, volatile T6*, volatile T7*>
181 smem_tuple(T0* t0, T1* t1, T2* t2, T3* t3, T4* t4, T5* t5, T6* t6, T7* t7)
183 return thrust::make_tuple((volatile T0*) t0, (volatile T1*) t1, (volatile T2*) t2, (volatile T3*) t3, (volatile T4*) t4, (volatile T5*) t5, (volatile T6*) t6, (volatile T7*) t7);
186 template <typename T0, typename T1, typename T2, typename T3, typename T4, typename T5, typename T6, typename T7, typename T8>
188 thrust::tuple<volatile T0*, volatile T1*, volatile T2*, volatile T3*, volatile T4*, volatile T5*, volatile T6*, volatile T7*, volatile T8*>
189 smem_tuple(T0* t0, T1* t1, T2* t2, T3* t3, T4* t4, T5* t5, T6* t6, T7* t7, T8* t8
[all...] |
| /external/opencv3/modules/cudev/include/opencv2/cudev/warp/ |
| reduce.hpp | 183 template <typename T0, typename T1, typename T2, typename T3, typename T4, typename T5, typename T6, typename T7>
185 tuple<volatile T0*, volatile T1*, volatile T2*, volatile T3*, volatile T4*, volatile T5*, volatile T6*, volatile T7*>
186 smem_tuple(T0* t0, T1* t1, T2* t2, T3* t3, T4* t4, T5* t5, T6* t6, T7* t7)
188 return make_tuple((volatile T0*) t0, (volatile T1*) t1, (volatile T2*) t2, (volatile T3*) t3, (volatile T4*) t4, (volatile T5*) t5, (volatile T6*) t6, (volatile T7*) t7);
191 template <typename T0, typename T1, typename T2, typename T3, typename T4, typename T5, typename T6, typename T7, typename T8>
193 tuple<volatile T0*, volatile T1*, volatile T2*, volatile T3*, volatile T4*, volatile T5*, volatile T6*, volatile T7*, volatile T8*>
194 smem_tuple(T0* t0, T1* t1, T2* t2, T3* t3, T4* t4, T5* t5, T6* t6, T7* t7, T8* t8
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| at-1.d | 422 [0-9a-f]+ <[^>]*> lui t7,0x1
423 [0-9a-f]+ <[^>]*> addu t7,t7,k1
424 [0-9a-f]+ <[^>]*> lw k1,-32768\(t7\)
425 [0-9a-f]+ <[^>]*> lui t7,0x1
426 [0-9a-f]+ <[^>]*> addu t7,t7,k1
427 [0-9a-f]+ <[^>]*> sw k1,-32768\(t7\)
428 [0-9a-f]+ <[^>]*> lui t7,0xffff
429 [0-9a-f]+ <[^>]*> addu t7,t7,k
[all...] |
| micromips@mips32.d | 17 [0-9a-f]+ <[^>]*> 01ee 6a10 mul t5,t6,t7
|
| /external/clang/test/CodeGen/ |
| asm.c | 40 void t7(int a) { function
41 __asm__ volatile("T7 NAMED: %[input]" : "+r"(a): [input] "i" (4));
42 // CHECK: @t7(i32
43 // CHECK: T7 NAMED: $1
|
| libcalls-fno-builtin.c | 55 char *t7(char *x) { return strncat(x, "", 1); } function
56 // CHECK: t7
|
| /external/clang/test/CodeGenCXX/ |
| new.cpp | 87 void t7() { function
|
| /external/clang/test/Misc/ |
| integer-literal-printing.cpp | 76 struct Type7<wcharTy::c, "7"> t7; // expected-error{{value of type 'const char [2]' is not implicitly convertible to 'typename Type7Helper<(wcharTy)L'\x00'>::Ty' (aka 'wcharTy')}} local
|
| /external/clang/test/Sema/ |
| ms-inline-asm.c | 119 void t7() { function
|
| unused-expr.c | 99 int t7 __attribute__ ((warn_unused_result)); // expected-warning {{'warn_unused_result' attribute only applies to functions}}
|
| /external/clang/test/SemaCXX/ |
| vararg-non-pod.cpp | 119 void t7(int n, ...) { function
|
| abstract.cpp | 79 void t7(Abstract a);
|
| /external/icu/icu4j/tools/misc/src/com/ibm/icu/dev/tool/translit/ |
| WriteIndicCharts.java | 76 Transliterator t7 = Transliterator.getInstance("InterIndic-Kannada"); local
99 writeIICharts(t7,0x0C80,8);
200 Transliterator t7 = Transliterator.getInstance("InterIndic-Kannada"); local
222 writeCharts(t7,knda,7);
233 writeCharts(t7,0x0C80,8);
243 writeIICharts(t7,0x0C80,8);
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 14 ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
32 seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 25 msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
30 seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/src/mips/ |
| codegen-mips.cc | 197 __ lw(t7, MemOperand(a1, 7, loadstore_chunk));
207 __ sw(t7, MemOperand(a0, 7, loadstore_chunk));
216 __ lw(t7, MemOperand(a1, 15, loadstore_chunk));
226 __ sw(t7, MemOperand(a0, 15, loadstore_chunk));
247 __ lw(t7, MemOperand(a1, 7, loadstore_chunk));
256 __ sw(t7, MemOperand(a0, 7, loadstore_chunk));
361 __ lwr(t7, MemOperand(a1, 7, loadstore_chunk));
376 __ lwl(t7,
396 __ lwl(t7, MemOperand(a1, 7, loadstore_chunk));
411 __ lwr(t7,
[all...] |
| /bionic/libm/upstream-freebsd/lib/msun/src/ |
| e_lgammaf_r.c | 53 t7 = -9.89206228e-03, /* 0xbc221251 */ variable
179 p = t0+y*t1+y*y*(t2+y*(t3+y*(t4+y*(t5+y*(t6+y*t7)))));
|
| e_lgamma_r.c | 118 t7 = -3.68452016781138256760e-03, /* 0xBF6E2EFF, 0xB3E914D7 */ variable
261 p2 = t1+w*(t4+w*(t7+w*(t10+w*t13)));
|
| /external/opencv3/modules/cudaimgproc/src/cuda/ |
| debayer.cu | 90 const int t7 = (patch[0][1].w + patch[1][1].z + patch[1][2].x + patch[2][1].w + 2) >> 2;
107 res3.y = t7;
125 res3.y = t7;
141 const int t7 = (patch[1][1].z + patch[1][2].x + 1) >> 1;
157 res3.x = t7;
177 res3.z = t7;
|
| /external/llvm/include/llvm/Support/ |
| AlignOf.h | 194 typename T5 = char, typename T6 = char, typename T7 = char,
197 T1 t1; T2 t2; T3 t3; T4 t4; T5 t5; T6 t6; T7 t7; T8 t8; T9 t9; T10 t10; member in class:llvm::detail::AlignerImpl
204 typename T5 = char, typename T6 = char, typename T7 = char,
208 arr5[sizeof(T5)], arr6[sizeof(T6)], arr7[sizeof(T7)], arr8[sizeof(T8)],
222 typename T5 = char, typename T6 = char, typename T7 = char,
226 T6, T7, T8, T9, T10> >::Alignment,
228 T6, T7, T8, T9, T10>)> {
|
| /external/llvm/test/MC/Mips/ |
| mips_directives.s | 51 .set STORE_MASK,$t7
|
| /external/valgrind/coregrind/m_syswrap/ |
| priv_types_n_macros.h | 602 #define PRE_REG_READ7(tr, s, t1, a1, t2, a2, t3, a3, t4, a4, t5, a5, t6, a6, t7, a7) \
607 PRA7(s,t7,a7); \
610 #define PRE_REG_READ8(tr, s, t1, a1, t2, a2, t3, a3, t4, a4, t5, a5, t6, a6, t7, a7, t8, a8) \
615 PRA7(s,t7,a7); PRA8(s,t8,a8); \
|
