| /art/disassembler/ |
| disassembler_x86.cc | 294 const char* opcode1 = ""; // Main opcode. local
316 case rm8_r8: opcode1 = #opname; store = true; has_modrm = true; byte_operand = true; break; \
317 case rm32_r32: opcode1 = #opname; store = true; has_modrm = true; break; \
318 case r8_rm8: opcode1 = #opname; load = true; has_modrm = true; byte_operand = true; break; \
319 case r32_rm32: opcode1 = #opname; load = true; has_modrm = true; break; \
320 case ax8_i8: opcode1 = #opname; ax = true; immediate_bytes = 1; byte_operand = true; break; \
321 case ax32_i32: opcode1 = #opname; ax = true; immediate_bytes = 4; break;
358 opcode1 = "push";
363 opcode1 = "pop";
369 opcode1 = "movsxd"
[all...] |
| disassembler_arm.cc | 1605 uint16_t opcode1 = instr >> 10; local
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| maverick.c | 183 #define CDP2(insname, var, cpnum, opcode1, opcode2, reg1name, reg2name) \
185 (14 << 24) | ((opcode1) << 20) | ((cpnum) << 8) | ((opcode2) << 5), \
189 #define CDP2fx(insname, opcode1, opcode2) \
190 CDP2 (insname, 32, 5, opcode1, opcode2, "fx", "fx")
193 #define CDP2dx(insname, opcode1, opcode2) \
194 CDP2 (insname, 64, 5, opcode1, opcode2, "dx", "dx")
197 #define CDP2f(insname, opcode1, opcode2) \
198 CDP2 (insname, s, 4, opcode1, opcode2, "f", "f")
201 #define CDP2d(insname, opcode1, opcode2) \
202 CDP2 (insname, d, 4, opcode1, opcode2, "d", "d"
[all...] |
| /external/llvm/tools/llvm-readobj/ |
| ARMEHABIPrinter.h | 108 uint8_t Opcode1 = Opcodes[OI++ ^ 3];
110 uint16_t GPRMask = (Opcode1 << 4) | ((Opcode0 & 0x0f) << 12);
113 Opcode0, Opcode1, GPRMask ? "pop " : "refuse to unwind");
149 uint8_t Opcode1 = Opcodes[OI++ ^ 3];
152 << format("0x%02X 0x%02X ; %s", Opcode0, Opcode1,
153 ((Opcode1 & 0xf0) || Opcode1 == 0x00) ? "spare" : "pop ");
154 if (((Opcode1 & 0xf0) == 0x00) && Opcode1)
155 PrintGPR((Opcode1 & 0x0f))
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/rawdex/ |
| Opcode.java | 277 public static boolean isBetween(Opcode opcode, Opcode opcode1, Opcode opcode2) {
278 return (opcode.ordinal() >= opcode1.ordinal() && opcode.ordinal() <= opcode2.ordinal());
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-d30v.c | 935 write_2_short (struct d30v_insn *opcode1,
947 && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR))
948 && ((opcode1->op->flags_used & FLAG_DELAY) == 0)
949 && ((opcode1->ecc == ECC_AL) || ! Optimizing))
956 write_1_short (opcode1, insn1, fx->next, FALSE);
967 && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)
968 && ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU
969 || opcode1->op->unit == MU)
977 if (opcode1->op->unit == IU
987 else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR
[all...] |
| tc-microblaze.c | 889 struct op_code_struct * opcode, *opcode1; local
1089 opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
1090 if (opcode1 == NULL)
1096 inst1 = opcode1->bit_sequence;
1963 struct op_code_struct * opcode1; local
[all...] |
| tc-d10v.c | 958 write_2_short (struct d10v_opcode *opcode1,
970 && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY)))
973 if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
979 if (opcode1->exec_type & ALONE)
982 write_1_short (opcode1, insn1, fx->next);
986 && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
989 if (opcode1->unit == IU)
996 else if (opcode1->unit == IU)
997 /* Reverse sequential with IU opcode1 on right and done first. */
1000 /* Sequential with non-IU opcode1 on left and done first. *
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrFormats.td | 68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
78 let Inst{0-5} = opcode1;
287 class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
307 class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2,
310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2,
1096 class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk,
1100 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> {
1123 class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1,
1128 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrFormats.td | [all...] |
| /toolchain/binutils/binutils-2.25/gas/doc/ |
| c-xtensa.texi | 141 @var{opcode1} [@var{operands}]
161 @{ [@var{format};] @var{opcode0} [@var{operands}]; @var{opcode1} [@var{operands}]; @var{opcode2} [@var{operands}]; @dots{} @}
[all...] |
| /hardware/intel/img/psb_video/src/mrst/ |
| psb_MPEG4.c | [all...] |
| /hardware/intel/img/psb_video/src/ |
| pnw_MPEG4.c | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 236 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode1,
239 (cast<Instruction>(V)->getOpcode() == Opcode1 ||
[all...] |
| /toolchain/binutils/binutils-2.25/gas/ |
| ChangeLog-0001 | [all...] |
| /toolchain/binutils/binutils-2.25/gas/po/ |
| ja.po | [all...] |
| ru.po | [all...] |
| rw.po | [all...] |
