| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/xc16x/ |
| andb.s | 4 andb rl0,rl1
5 andb rl0,[r1]
6 andb rl0,[r1+]
7 andb rl0,#3
8 andb rl0,#0xbe
9 andb rl0,0x0230
10 andb 0x320,rl0
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/ |
| and_test.s | 5 # ANDB imm4/imm16, reg
7 andb $0xf,r1
8 andb $0xff,r2
9 andb $0xfff,r1
10 andb $0xffff,r2
11 andb $20,r1
12 andb $10,r2
14 # ANDB reg, reg
16 andb r1,r2
17 andb r2,r
[all...] |
| and_test.d | 10 0: f1 20 andb \$0xf:s,r1
11 2: b2 20 ff 00 andb \$0xff:m,r2
12 6: b1 20 ff 0f andb \$0xfff:m,r1
13 a: b2 20 ff ff andb \$0xffff:m,r2
14 e: b1 20 14 00 andb \$0x14:m,r1
15 12: a2 20 andb \$0xa:s,r2
16 14: 12 21 andb r1,r2
17 16: 23 21 andb r2,r3
18 18: 34 21 andb r3,r4
19 1a: 56 21 andb r5,r
[all...] |
| /art/runtime/interpreter/mterp/x86/ |
| op_array_length.S | 9 andb $$0xf, %al # eax <- A
|
| op_mul_int_2addr.S | 5 andb $$0xf, %cl # ecx <- A
|
| fpcvt.S | 9 andb $$0xf, %cl # ecx <- A
|
| op_iget_wide_quick.S | 9 andb $$0xf, rINSTbl # rINST <- A
|
| op_int_to_long.S | 5 andb $$0xf, rINSTbl # rINST <- A
|
| op_move.S | 5 andb $$0xf, %al # eax <- A
|
| op_move_wide.S | 5 andb $$0xf, %cl # ecx <- A
|
| op_mul_int_lit16.S | 8 andb $$0xf, rINSTbl # rINST <- A
|
| op_not_long.S | 4 andb $$0xf, rINSTbl # rINST <- A
|
| op_rem_double_2addr.S | 5 andb $$0xf, %cl # ecx <- A
|
| op_rem_float_2addr.S | 5 andb $$0xf, %cl # ecx <- A
|
| shop2addr.S | 9 andb $$0xf, rINSTbl # rINST <- A
|
| unop.S | 10 andb $$0xf,%cl # ecx <- A
|
| /art/runtime/interpreter/mterp/x86_64/ |
| binopWide2addr.S | 7 andb $$0xf, %cl # ecx <- A
|
| op_array_length.S | 9 andb $$0xf, %al # eax <- A
|
| op_int_to_long.S | 4 andb $$0xf, rINSTbl # rINST <- A
|
| op_mul_int_2addr.S | 4 andb $$0xf, %cl # ecx <- A
|
| op_mul_long_2addr.S | 4 andb $$0xf, %cl # ecx <- A
|
| op_iput_wide.S | 8 andb $$0xf, rINSTbl # rINST <- A
|
| op_move.S | 5 andb $$0xf, %al # eax <- A
|
| /external/llvm/test/CodeGen/SystemZ/ |
| risbg-03.ll | 11 %andb = and i64 %b, 14
12 %or = or i64 %anda, %andb
23 %andb = and i64 %b, 14
24 %or = or i64 %anda, %andb
|
| risbg-02.ll | 11 %andb = and i32 %b, 14
12 %or = or i32 %anda, %andb
22 %andb = and i64 %b, 14
23 %or = or i64 %anda, %andb
34 %andb = and i32 %shr, 15
35 %or = or i32 %anda, %andb
46 %andb = and i64 %shr, 15
47 %or = or i64 %anda, %andb
|
