| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| r6.s | 184 bltc $2, $3, ext
185 bltc $2, $3, . + 4 + (-32768 << 2)
186 bltc $2, $3, . + 4 + (32767 << 2)
187 bltc $2, $3, 1f
188 bltc $3, $2, 1f
|
| r6-n32.d | 334 0+03e0 <[^>]*> 5c430000 bltc v0,v1,000003e4 <[^>]*>
337 0+03e8 <[^>]*> 5c430000 bltc v0,v1,000003ec <[^>]*>
340 0+03f0 <[^>]*> 5c430000 bltc v0,v1,000003f4 <[^>]*>
343 0+03f8 <[^>]*> 5c430000 bltc v0,v1,000003fc <[^>]*>
346 0+0400 <[^>]*> 5c620000 bltc v1,v0,00000404 <[^>]*>
|
| r6.d | 333 0+03e0 <[^>]*> 5c43ffff bltc v0,v1,000003e0 <[^>]*>
336 0+03e8 <[^>]*> 5c438000 bltc v0,v1,fffe03ec <[^>]*>
339 0+03f0 <[^>]*> 5c437fff bltc v0,v1,000203f0 <[^>]*>
342 0+03f8 <[^>]*> 5c43ffff bltc v0,v1,000003f8 <[^>]*>
345 0+0400 <[^>]*> 5c62ffff bltc v1,v0,00000400 <[^>]*>
|
| r6-n64.d | 484 0+03e0 <[^>]*> 5c430000 bltc v0,v1,0+03e4 <[^>]*>
489 0+03e8 <[^>]*> 5c430000 bltc v0,v1,0+03ec <[^>]*>
494 0+03f0 <[^>]*> 5c430000 bltc v0,v1,0+03f4 <[^>]*>
499 0+03f8 <[^>]*> 5c430000 bltc v0,v1,0+03fc <[^>]*>
504 0+0400 <[^>]*> 5c620000 bltc v1,v0,0+0404 <[^>]*>
|
| /art/runtime/interpreter/mterp/mips64/ |
| header.S | 31 * idioms, which should translate into bgec and bltc respectively with swapped
39 bltc \rreg, \lreg, \target
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 390 COMPARE_PC_REL_COMPACT(bltc(a0, a1, -32768),
391 "5c858000 bltc a0, a1, -32768", -32768);
392 COMPARE_PC_REL_COMPACT(bltc(a0, a1, -1),
393 "5c85ffff bltc a0, a1, -1", -1);
394 COMPARE_PC_REL_COMPACT(bltc(a0, a1, 1), "5c850001 bltc a0, a1, 1",
396 COMPARE_PC_REL_COMPACT(bltc(a0, a1, 32767),
397 "5c857fff bltc a0, a1, 32767", 32767);
[all...] |
| test-disasm-mips64.cc | [all...] |
| /external/v8/src/mips/ |
| constants-mips.cc | 141 case BGTZL: // POP27 bgtzc, bltzc, bltc/bgtc
|
| assembler-mips.h | 643 void bltc(Register rs, Register rt, int16_t offset);
644 inline void bltc(Register rs, Register rt, Label* L) {
645 bltc(rs, rt, shifted_branch_offset(L));
[all...] |
| /external/v8/src/mips64/ |
| constants-mips64.cc | 141 case BGTZL: // POP27 bgtzc, bltzc, bltc/bgtc
|
| assembler-mips64.h | 647 void bltc(Register rs, Register rt, int16_t offset);
648 inline void bltc(Register rs, Register rt, Label* L) {
649 bltc(rs, rt, shifted_branch_offset(L));
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 221 void Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
339 void Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label);
|
| assembler_mips64.cc | 554 void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16) {
640 Bltc(rs, rt, imm16_21);
649 Bltc(rt, rs, imm16_21);
[all...] |
| assembler_mips64_test.cc | 718 TEST_F(AssemblerMIPS64Test, Bltc) {
719 BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bltc, "Bltc");
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| valid-mips32r6-el.txt | 37 0x40 0x00 0xa6 0x5c # CHECK: bltc $5, $6, 256
|
| valid-mips32r6.txt | 151 0x5c 0xa6 0x00 0x40 # CHECK: bltc $5, $6, 256
|