| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_cpu_detect.c | 258 util_cpu_caps.cacheline = 32;
264 unsigned int cacheline; local
284 cacheline = ((regs2[1] >> 8) & 0xFF) * 8;
285 if (cacheline > 0)
286 util_cpu_caps.cacheline = cacheline;
303 util_cpu_caps.cacheline = regs2[2] & 0xFF;
324 debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline);
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| u_cpu_detect.h | 53 unsigned cacheline; member in struct:util_cpu_caps
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| /external/jemalloc/src/ |
| ckh.c | 268 usize = sa2u(sizeof(ckhc_t) << lg_curcells, CACHELINE);
273 tab = (ckhc_t *)ipallocztm(tsd, usize, CACHELINE, true, NULL,
314 usize = sa2u(sizeof(ckhc_t) << lg_curcells, CACHELINE);
317 tab = (ckhc_t *)ipallocztm(tsd, usize, CACHELINE, true, NULL, true,
389 usize = sa2u(sizeof(ckhc_t) << lg_mincells, CACHELINE);
394 ckh->tab = (ckhc_t *)ipallocztm(tsd, usize, CACHELINE, true, NULL, true,
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| base.c | 87 * Round size up to nearest multiple of the cacheline size, so that
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| tcache.c | 325 /* Avoid false cacheline sharing. */
326 size = sa2u(size, CACHELINE);
328 tcache = ipallocztm(tsd, size, CACHELINE, true, false, true,
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| huge.c | 61 CACHELINE, false, tcache, true, arena);
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| /external/kernel-headers/original/uapi/linux/ |
| target_core_user.h | 53 /* Updated by user. On its own cacheline */
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| /external/libunwind/tests/ |
| Gperf-trace.c | 143 char padding[1024]; /* should be > 2 * max. cacheline size */
149 char padding[1024]; /* should be > 2 * max. cacheline size */
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| Gperf-simple.c | 157 char padding[1024]; /* should be > 2 * max. cacheline size */
163 char padding[1024]; /* should be > 2 * max. cacheline size */
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| /prebuilts/misc/darwin-x86_64/sdl2/include/SDL2/ |
| SDL_cpuinfo.h | 72 /* This is a guess for the cacheline size used for padding.
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| /prebuilts/misc/windows/sdl2/i686-w64-mingw32/include/SDL2/ |
| SDL_cpuinfo.h | 72 /* This is a guess for the cacheline size used for padding.
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| /prebuilts/misc/windows/sdl2/include/ |
| SDL_cpuinfo.h | 72 /* This is a guess for the cacheline size used for padding.
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| /prebuilts/misc/windows/sdl2/x86_64-w64-mingw32/include/SDL2/ |
| SDL_cpuinfo.h | 72 /* This is a guess for the cacheline size used for padding.
|
| /external/valgrind/helgrind/ |
| libhb_core.c | 88 # define CHECK_ZSM 1 /* do sanity-check CacheLine stuff */
92 # define CHECK_ZSM 0 /* don't sanity-check CacheLine stuff */
439 /* ------ CacheLine ------ */
450 CacheLine;
506 CacheLine-sized chunks of SecMaps are copied into a Cache, being
564 /* Each tag is the address of the associated CacheLine, rounded down
565 to a CacheLine address boundary. A CacheLine size must be a power
573 CacheLine lyns0[N_WAY_NENT];
580 a CacheLine. *
[all...] |
| /external/jemalloc/include/jemalloc/internal/ |
| tcache.h | 86 * To make use of adjacent cacheline prefetch, the items in the avail
281 * (waiting for the cacheline).
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| jemalloc_internal.h | 301 * In addition, this controls the spacing of cacheline-spaced size classes.
303 * CACHELINE cannot be based on LG_CACHELINE because __declspec(align()) can
307 #define CACHELINE 64
308 #define CACHELINE_MASK (CACHELINE - 1)
310 /* Return the smallest cacheline multiple that is >= s. */
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| jemalloc_internal.h.in | 301 * In addition, this controls the spacing of cacheline-spaced size classes.
303 * CACHELINE cannot be based on LG_CACHELINE because __declspec(align()) can
307 #define CACHELINE 64
308 #define CACHELINE_MASK (CACHELINE - 1)
310 /* Return the smallest cacheline multiple that is >= s. */
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 194 // TODO: Make the loads schedule near if it fits in a cacheline
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| /prebuilts/gcc/darwin-x86/host/i686-apple-darwin-4.2.1/include/gcc/darwin/4.2/ |
| ppc_intrinsics.h | 312 * cacheline is
316 * of the cacheline to be operated on.
318 * Effective Address of cacheline to be manipulated =
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| /bionic/libc/arch-arm/cortex-a15/bionic/ |
| memcpy_base.S | 196 // than loads that cross a cacheline boundary.
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| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstrInfo.cpp | 213 // A cacheline is 64 bytes (for global memory).
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_urb.c | 251 /* erratum: URB_FENCE must not cross a 64byte cacheline */
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| /libcore/luni/src/main/java/java/util/concurrent/ |
| Exchanger.java | 125 * writing, there is no way to determine cacheline size, we define
227 * in the arena. 1 << ASHIFT should be at least cacheline size.
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| /external/opencv3/3rdparty/libwebp/dec/ |
| vp8i.h | 95 // With this layout, BPS (=Bytes Per Scan-line) is one cacheline size.
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| /external/webp/src/dec/ |
| vp8i.h | 37 // YUV-cache parameters. Cache is 32-bytes wide (= one cacheline).
|
