| /external/valgrind/none/tests/mips64/ |
| move_instructions.stdout.exp-BE | 2 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
4 dmtc1, mov.d, dmfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
6 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
8 dmtc1, mov.d, dmfc1 :: mem: 0x7e876382d2ab13 out: 0x7e876382d2ab13
10 dmtc1, mov.d, dmfc1 :: mem: 0x9823b6e out: 0x9823b6e
12 dmtc1, mov.d, dmfc1 :: mem: 0x976d6e9ac31510f3 out: 0x976d6e9ac31510f3
14 dmtc1, mov.d, dmfc1 :: mem: 0xd4326d9 out: 0xd4326d9
16 dmtc1, mov.d, dmfc1 :: mem: 0xb7746d775ad6a5fb out: 0xb7746d775ad6a5fb
18 dmtc1, mov.d, dmfc1 :: mem: 0x130476dc out: 0x130476dc
20 dmtc1, mov.d, dmfc1 :: mem: 0x42b0c0a28677b502 out: 0x42b0c0a28677b50
[all...] |
| move_instructions.stdout.exp-LE | 2 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
4 dmtc1, mov.d, dmfc1 :: mem: 0x12bd6aa out: 0x12bd6aa
6 dmtc1, mov.d, dmfc1 :: mem: 0x0 out: 0x0
8 dmtc1, mov.d, dmfc1 :: mem: 0x7e876382d2ab13 out: 0x7e876382d2ab13
10 dmtc1, mov.d, dmfc1 :: mem: 0x9823b6e out: 0x9823b6e
12 dmtc1, mov.d, dmfc1 :: mem: 0x976d6e9ac31510f3 out: 0x976d6e9ac31510f3
14 dmtc1, mov.d, dmfc1 :: mem: 0xd4326d9 out: 0xd4326d9
16 dmtc1, mov.d, dmfc1 :: mem: 0xb7746d775ad6a5fb out: 0xb7746d775ad6a5fb
18 dmtc1, mov.d, dmfc1 :: mem: 0x130476dc out: 0x130476dc
20 dmtc1, mov.d, dmfc1 :: mem: 0x42b0c0a28677b502 out: 0x42b0c0a28677b50
[all...] |
| load_store_unaligned.c | 35 "dmfc1 %0, $f0" "\n\t"
|
| macro_load_store.h | 56 "dmfc1 %0, $f0" "\n\t" \
112 "dmfc1 %0, $f0" "\n\t" \
|
| macro_fpu.h | 151 "dmfc1 %1, $f0" "\n\t" \
173 "dmfc1 %1, $f0" "\n\t" \
|
| move_instructions.c | 80 "dmfc1 $t1, $f0" "\n\t" \
88 printf("dmtc1, mov.d, dmfc1 :: mem: 0x%llx out: 0x%llx\n", \
130 "dmfc1 %0, $"#FD "\n\t" \
169 "dmfc1 %0, $"#FD "\n\t" \
|
| /art/runtime/interpreter/mterp/mips64/ |
| op_double_to_long.S | 18 dmfc1 t0, f0
|
| op_float_to_long.S | 18 dmfc1 t0, f0
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64-libcall.ll | 9 ; HARD-NOT: dmfc1 $4
|
| fpxx.ll | 208 ; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
211 ; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
215 ; floats/doubles are not passed in integer registers for n64, so dmfc1 is not used.
218 ; constraint 'r'". It therefore seems impossible to test the generation of dmfc1
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| micromips.s | [all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 22 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 22 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 22 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/src/compiler/mips64/ |
| code-generator-mips64.cc | 443 __ dmfc1(at, i.OutputDoubleRegister()); \
[all...] |
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 26 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 24 dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 24 dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrFPU.td | 382 def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64-el.txt | 86 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
227 0x00 0x70 0x22 0x44 # CHECK: dmfc1 $2, $f14
|
| valid-mips64.txt | 207 0x44 0x22 0x70 0x00 # CHECK: dmfc1 $2, $f14
208 0x44 0x2c 0x68 0x00 # CHECK: dmfc1 $12, $f13
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2-el.txt | 92 0x00 0x68 0x2c 0x44 # CHECK: dmfc1 $12, $f13
248 0x00 0x70 0x22 0x44 # CHECK: dmfc1 $2, $f14
|
| /external/v8/src/mips64/ |
| macro-assembler-mips64.cc | [all...] |
| /art/compiler/optimizing/ |
| intrinsics_mips64.cc | 154 __ Dmfc1(out, in);
745 __ Dmfc1(AT, out);
767 __ Dmfc1(AT, out);
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 310 void Dmfc1(GpuRegister rt, FpuRegister fs); // MIPS64
|
