/prebuilts/go/darwin-x86/test/dwarf/dwarf.dir/ |
z18.go | 5 func F18() {}
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/prebuilts/go/linux-x86/test/dwarf/dwarf.dir/ |
z18.go | 5 func F18() {}
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/sparc/ |
ima.s | 4 fpmaddxhi %f14, %f8, %f38, %f18
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ima.d | 11 4: a5 bb 8e 88 fpmaddxhi %f14, %f8, %f38, %f18
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sparc5vis4.s | 8 fpaddus16 %f16, %f18, %f20 15 fpmax8 %f14, %f16, %f18 16 fpmax16 %f18, %f20, %f22 30 fpsubus16 %f14, %f16, %f18
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hpcvis3.s | 20 fmaddd %f14, %f16, %f18, %f20 22 fmsubd %f16, %f18, %f20, %f22 24 fnmsubd %f18, %f20, %f22, %f24 63 fpsubs32s %f14, %f16, %f18 71 fucmple8 %f16, %f18, %g1 72 fucmpne8 %f18, %f20, %g2 81 flcmpd %fcc2, %f16, %f18 82 flcmpd %fcc3, %f18, %f20
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crypto.s | 13 aes_eround23 %f12, %f14, %f16, %f18 14 aes_dround01 %f14, %f16, %f18, %f20 15 aes_dround23 %f16, %f18, %f20, %f22 16 aes_eround01_l %f18, %f20, %f22, %f24
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sparc5vis4.d | 15 14: a9 b4 24 72 fpaddus16 %f16, %f18, %f20 22 30: a5 b3 a3 b0 fpmax8 %f14, %f16, %f18 23 34: ad b4 a3 d4 fpmax16 %f18, %f20, %f22 37 6c: a5 b3 aa 70 fpsubus16 %f14, %f16, %f18
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
mipsr6@mips5-fp.s | 4 cvt.s.pl $f16, $f18 5 cvt.s.pu $f18, $f20
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mipsr6@mips5-fp.d | 10 0+0000 <[^>]*> 46c09428 cvt\.s\.pl \$f16,\$f18 11 0+0004 <[^>]*> 46c0a4a0 cvt\.s\.pu \$f18,\$f20
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loongson-3a.s | 28 paddd $f18, $f19, $f20
38 pcmpeqw $f18, $f19, $f20
48 pmaxsh $f18, $f19, $f20
58 biadd $f17, $f18
69 psubd $f18, $f19, $f20
79 punpcklwd $f18, $f19, $f20
88 or $f18, $f19, $f20
98 sequ $f18, $f19
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loongson-2e.s | 30 nmadd.s $f18, $f19, $f20 44 paddd $f18, $f19, $f20 54 pcmpeqw $f18, $f19, $f20 64 pmaxsh $f18, $f19, $f20 74 biadd $f17, $f18 85 psubd $f18, $f19, $f20 95 punpcklwd $f18, $f19, $f20 104 or $f18, $f19, $f20 114 sequ $f18, $f19
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loongson-2f.s | 30 nmadd.s $f18, $f19, $f20 44 paddd $f18, $f19, $f20 54 pcmpeqw $f18, $f19, $f20 64 pmaxsh $f18, $f19, $f20 74 biadd $f17, $f18 85 psubd $f18, $f19, $f20 95 punpcklwd $f18, $f19, $f20 104 or $f18, $f19, $f20 114 sequ $f18, $f19
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/ |
simd.s | 9 pfzchkl %f8,%f10,%f18 12 pfzchks %f16,%f18,%f20 19 pfaddp %f8,%f10,%f18 22 pfaddz %f16,%f18,%f20 29 fzchkl %f4,%f6,%f18 33 fzchks %f16,%f18,%f20 39 faddp %f4,%f6,%f18 43 faddz %f16,%f18,%f20 48 d.pfzchkl %f0,%f2,%f18 59 d.pfzchks %f16,%f18,%f [all...] |
dir-align01.s | 9 pfadd.sd %f17,%f18,%f20
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form.s | 11 pform %f16,%f18 22 form %f16,%f18 38 d.pform %f16,%f18 58 d.form %f16,%f18
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float01.s | 16 fmul.dd %f18,%f20,%f22 22 pfadd.sd %f17,%f18,%f20 54 d.fmul.dd %f18,%f20,%f22 63 d.pfadd.sd %f17,%f18,%f20
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simd.d | 13 c: d7 45 52 49 pfzchkl %f8,%f10,%f18 15 14: df 85 54 4a pfzchks %f16,%f18,%f20 21 2c: d0 45 52 49 pfaddp %f8,%f10,%f18 23 34: d1 85 54 4a pfaddz %f16,%f18,%f20 28 48: d7 21 d2 48 fzchkl %f4,%f6,%f18 31 54: df 81 54 4a fzchks %f16,%f18,%f20 36 68: d0 21 d2 48 faddp %f4,%f6,%f18 39 74: d1 81 54 4a faddz %f16,%f18,%f20 42 80: d7 07 52 48 d.pfzchkl %f0,%f2,%f18 52 a8: df 87 46 4a d.pfzchks %f16,%f18,%f [all...] |
pfam.s | 28 i2pt.dd %f14,%f16,%f18 32 i2ap1.dd %f16,%f18,%f20 35 i2apt.sd %f17,%f18,%f19 36 i2apt.dd %f18,%f20,%f22 46 ra1p2.ss %f18,%f19,%f20 110 d.i2pt.dd %f14,%f16,%f18 117 d.i2ap1.dd %f16,%f18,%f20 122 d.i2apt.sd %f17,%f18,%f19 124 d.i2apt.dd %f18,%f20,%f22 141 d.ra1p2.ss %f18,%f19,%f2 [all...] |
pfmam.s | 28 mi2pt.dd %f14,%f16,%f18 32 mi2mp1.dd %f16,%f18,%f20 35 mi2mpt.sd %f17,%f18,%f19 36 mi2mpt.dd %f18,%f20,%f22 46 mrm1p2.ss %f18,%f19,%f20 110 d.mi2pt.dd %f14,%f16,%f18 117 d.mi2mp1.dd %f16,%f18,%f20 122 d.mi2mpt.sd %f17,%f18,%f19 124 d.mi2mpt.dd %f18,%f20,%f22 141 d.mrm1p2.ss %f18,%f19,%f2 [all...] |
pfmsm.s | 28 mi2st.dd %f14,%f16,%f18 32 mi2ms1.dd %f16,%f18,%f20 35 mi2mst.sd %f17,%f18,%f19 36 mi2mst.dd %f18,%f20,%f22 46 mrm1s2.ss %f18,%f19,%f20 110 d.mi2st.dd %f14,%f16,%f18 117 d.mi2ms1.dd %f16,%f18,%f20 122 d.mi2mst.sd %f17,%f18,%f19 124 d.mi2mst.dd %f18,%f20,%f22 141 d.mrm1s2.ss %f18,%f19,%f2 [all...] |
pfsm.s | 28 i2st.dd %f14,%f16,%f18 32 i2as1.dd %f16,%f18,%f20 35 i2ast.sd %f17,%f18,%f19 36 i2ast.dd %f18,%f20,%f22 46 ra1s2.ss %f18,%f19,%f20 110 d.i2st.dd %f14,%f16,%f18 117 d.i2as1.dd %f16,%f18,%f20 122 d.i2ast.sd %f17,%f18,%f19 124 d.i2ast.dd %f18,%f20,%f22 141 d.ra1s2.ss %f18,%f19,%f2 [all...] |
/external/valgrind/none/tests/ppc32/ |
test_dfp3.c | 34 register double f18 __asm__ ("fr18"); 91 __asm__ __volatile__ ("drintx 1, %0, %1, 0" : "=f" (f18) : "f" (f16)); 93 __asm__ __volatile__ ("drintx 0, %0, %1, 0" : "=f" (f18) : "f" (f16)); 97 __asm__ __volatile__ ("drintx 1, %0, %1, 1" : "=f" (f18) : "f" (f16)); 99 __asm__ __volatile__ ("drintx 0, %0, %1, 1" : "=f" (f18) : "f" (f16)); 103 __asm__ __volatile__ ("drintx 1, %0, %1, 2" : "=f" (f18) : "f" (f16)); 105 __asm__ __volatile__ ("drintx 0, %0, %1, 2" : "=f" (f18) : "f" (f16)); 109 __asm__ __volatile__ ("drintx 1, %0, %1, 3" : "=f" (f18) : "f" (f16)); 111 __asm__ __volatile__ ("drintx 0, %0, %1, 3" : "=f" (f18) : "f" (f16)); 127 __asm__ __volatile__ ("drintn 1, %0, %1, 0" : "=f" (f18) : "f" (f16)) [all...] |
test_dfp2.c | 39 register double f18 __asm__ ("fr18"); 116 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0)); 120 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1)); 124 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2)); 128 __asm__ __volatile__ ("dscri %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3)); 139 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_0)); 143 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_1)); 147 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_2)); 151 __asm__ __volatile__ ("dscli %0, %1, %2" : "=f" (f18) : "f" (f14), "i" (SH_3)); 160 __asm__ __volatile__ ("dctdp %0, %1" : "=f" (f18) : "f" (f14)) [all...] |
/external/llvm/test/MC/Mips/mips32r6/ |
invalid-mips32r2.s | 8 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 10 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 12 nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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