| /external/mesa3d/src/gallium/state_trackers/xa/ |
| xa_tgsi.c | 376 struct ureg_src imm0,
387 TGSI_SWIZZLE_Y), ureg_scalar(imm0,
391 TGSI_SWIZZLE_X, TGSI_SWIZZLE_Y), ureg_scalar(imm0,
405 ureg_scalar(imm0, TGSI_SWIZZLE_W));
425 ureg_scalar(imm0, TGSI_SWIZZLE_W));
437 struct ureg_src imm0 = { 0 }; local
474 imm0 = ureg_imm4f(ureg, 0, 0, 0, 1);
513 xrender_tex(ureg, src, src_input, src_sampler, imm0,
550 ureg_scalar(imm0, TGSI_SWIZZLE_X));
557 xrender_tex(ureg, mask, mask_pos, mask_sampler, imm0,
[all...] |
| /external/mesa3d/src/gallium/state_trackers/xorg/ |
| xorg_exa_tgsi.c | 397 struct ureg_src imm0,
410 ureg_scalar(imm0, TGSI_SWIZZLE_X));
416 ureg_scalar(imm0, TGSI_SWIZZLE_W));
430 ureg_scalar(imm0, TGSI_SWIZZLE_W));
450 ureg_scalar(imm0, TGSI_SWIZZLE_W));
463 struct ureg_src imm0 = { 0 }; local
502 imm0 = ureg_imm4f(ureg, 0, 0, 0, 1);
548 xrender_tex(ureg, src, src_input, src_sampler, imm0,
589 ureg_scalar(imm0, TGSI_SWIZZLE_X));
596 xrender_tex(ureg, mask, mask_pos, mask_sampler, imm0,
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_peephole.cpp | 390 ImmediateValue &imm0, ImmediateValue &imm1)
392 struct Storage *const a = &imm0.reg, *const b = &imm1.reg;
615 ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
623 tryCollapseChainedMULs(i, s, imm0);
625 if (imm0.isInteger(0)) {
631 if (imm0.isInteger(1) || imm0.isInteger(-1)) {
632 if (imm0.isNegative())
644 if (imm0.isInteger(2) || imm0.isInteger(-2))
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_tilegx_toIR.c | 597 ULong imm0 = decoded[n].operand_values[3]; local
598 ULong mask = ((-1ULL) ^ ((-1ULL << ((imm0 - imm) & 63)) << 1));
606 mkU8(imm0)),
630 ULong imm0 = decoded[n].operand_values[3]; local
633 mask = ((-1ULL) ^ ((-1ULL << ((imm0 - imm) & 63)) << 1));
651 ULong imm0 = decoded[n].operand_values[3]; local
654 if (imm <= imm0)
656 mask = ((-1ULL << imm) ^ ((-1ULL << imm0) << 1));
660 mask = ((-1ULL << imm) | (-1ULL >> (63 - imm0)));
[all...] |
| guest_tilegx_helpers.c | 244 case 152: /* mm rd, ra, imm0, imm1 */
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-opc-2.c | 71 {AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {}, "0"},
|
| aarch64-tbl.h | [all...] |
| ChangeLog | 764 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
|
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.cc | 393 // [imm3, imm2, imm1, imm0], where each imm is 16 bits.
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64.cc | 189 // [imm3, imm2, imm1, imm0], where each imm is 16 bits.
[all...] |
