| /external/llvm/test/CodeGen/AArch64/ |
| arm64-addrmode.ll | 6 ; base + offset (imm9)
16 ; base + offset (> imm9)
28 ; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
|
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 159 void Sc(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
160 void Scd(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
161 void Ll(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
162 void Lld(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
|
| assembler_mips64.cc | 320 void Mips64Assembler::Sc(GpuRegister rt, GpuRegister base, int16_t imm9) {
321 CHECK(IsInt<9>(imm9));
322 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x26);
325 void Mips64Assembler::Scd(GpuRegister rt, GpuRegister base, int16_t imm9) {
326 CHECK(IsInt<9>(imm9));
327 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x27);
330 void Mips64Assembler::Ll(GpuRegister rt, GpuRegister base, int16_t imm9) {
331 CHECK(IsInt<9>(imm9));
332 EmitI(0x1f, base, rt, ((imm9 & 0x1FF) << 7) | 0x36);
335 void Mips64Assembler::Lld(GpuRegister rt, GpuRegister base, int16_t imm9) {
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_arm64_toIR.c | 4711 UInt imm9 = INSN(20,12); local
5094 UInt imm9 = INSN(20,12); local
5172 UInt imm9 = INSN(20,12); local
5555 UInt imm9 = INSN(20,12); local
5601 UInt imm9 = INSN(20,12); local
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 1148 Instr Assembler::ImmLS(int imm9) {
1149 DCHECK(is_int9(imm9));
1150 return truncate_to_int9(imm9) << ImmLS_offset;
[all...] |
| assembler-arm64.h | [all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| nds32.h | 118 #define N16_TYPE9(op6, imm9) \
119 (0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9))
|
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.cpp | 1028 uint32_t imm9 = (unsigned)(simm) & 0x01FF; local
1029 return (0xB8 << 24) | (imm9 << 12) | (0x3 << 10) | (Rn << 5) | Rt;
1040 uint32_t imm9 = (unsigned)(simm) & 0x01FF; local
1042 (imm9 << 12) | (0x1 << 10) | (Rn << 5) | Rt;
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.h | 198 void LlR6(Register rt, Register base, int16_t imm9 = 0);
199 void ScR6(Register rt, Register base, int16_t imm9 = 0);
[all...] |
| assembler_mips.cc | 498 void MipsAssembler::LlR6(Register rt, Register base, int16_t imm9) {
500 CHECK(IsInt<9>(imm9));
501 EmitI(0x1f, base, rt, ((imm9 & 0x1ff) << 7) | 0x36);
504 void MipsAssembler::ScR6(Register rt, Register base, int16_t imm9) {
506 CHECK(IsInt<9>(imm9));
507 EmitI(0x1f, base, rt, ((imm9 & 0x1ff) << 7) | 0x26);
[all...] |
| /external/vixl/src/vixl/a64/ |
| assembler-a64.h | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-asm.c | 544 /* simm (imm9 or imm7) */
[all...] |
| v850-opc.c | 1171 /* The imm9 field in a multiply word. */
1175 /* The unsigned imm9 field in a multiply word. */
[all...] |
| aarch64-dis.c | 891 /* simm (imm9 or imm7) */
[all...] |
| aarch64-opc.c | 183 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
