| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic54x/ |
| subsym.s | 44 .word $isreg(SYMBOL) ; 0
45 .word $isreg("AR0") ;
46 ; .word $isreg("AG") ; should be 0, but we always
49 x .word $isreg("AG") ; 1 if .mmregs, 0 otherwise
|
| /external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 18 if (Op.isReg()) {
|
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) {
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
192 if (Op.isReg()) {
299 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) &&
301 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS));
304 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
307 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
310 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
313 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineOperand.h | 192 return isReg() ? 0 : SubReg_TargetFlags;
195 assert(!isReg() && "Register operands can't have target flags");
200 assert(!isReg() && "Register operands can't have target flags");
229 /// isReg - Tests if this is a MO_Register operand.
230 bool isReg() const { return OpKind == MO_Register; }
268 assert(isReg() && "This is not a register operand!");
273 assert(isReg() && "Wrong MachineOperand accessor");
278 assert(isReg() && "Wrong MachineOperand accessor");
283 assert(isReg() && "Wrong MachineOperand accessor");
288 assert(isReg() && "Wrong MachineOperand accessor")
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 67 assert(FoldOp->isReg());
111 assert(Old.isReg());
183 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() ||
184 !MI->getOperand(CommuteIdx1).isReg()))
208 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) ||
327 if (!FoldingImm && !OpToFold.isReg())
338 if (OpToFold.isReg() &&
368 assert(Fold.OpToFold && Fold.OpToFold->isReg());
|
| SIInstrInfo.cpp | 818 assert(SrcOp.isReg());
899 if (!Src0.isReg())
927 if (!Src1.isReg()) {
[all...] |
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI);
220 assert(MI.getOperand(OpNo+1).isReg());
239 assert(MI.getOperand(OpNo+1).isReg());
259 assert(MI.getOperand(OpNo+1).isReg());
275 assert(MI.getOperand(OpNo+1).isReg());
291 assert(MI.getOperand(OpNo+1).isReg());
[all...] |
| /external/llvm/lib/CodeGen/ |
| LivePhysRegs.cpp | 47 if (O->isReg()) {
60 if (!O->isReg() || !O->readsReg() || O->isUndef())
77 if (O->isReg()) {
98 if (Reg.second->isReg() && Reg.second->isDead())
|
| MachineInstr.cpp | 99 assert(isReg() && "Wrong MachineOperand accessor");
119 if (!isReg() || !isOnRegUseList())
134 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
143 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
152 assert((!isReg() || !isTied()) &&
164 assert((!isReg() || !isTied()) &&
186 bool WasReg = isReg();
698 if (MO.isReg())
707 if (MO.isReg())
754 bool isImpReg = Op.isReg() && Op.isImplicit()
[all...] |
| DeadMachineInstructionElim.cpp | 74 if (MO.isReg() && MO.isDef()) {
140 if (MO.isReg() && MO.isDef()) {
159 if (MO.isReg() && MO.isUse()) {
|
| ExpandPostRAPseudos.cpp | 74 if (!MO.isReg() || !MO.isImplicit() || MO.isUse())
82 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
84 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
|
| MachineInstrBundle.cpp | 62 if (MO.isReg() && MO.isInternalRead())
138 if (!MO.isReg())
269 if (!MO.isReg() || MO.getReg() != Reg)
308 if (!MO.isReg())
|
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| SparcInstPrinter.cpp | 62 if (!MI->getOperand(0).isReg())
86 || (!MI->getOperand(0).isReg())
112 if (MO.isReg()) {
139 if (MO.isReg() && MO.getReg() == SP::G0)
|
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCCodeEmitter.cpp | 119 if (MO.isReg())
146 if (MO.isReg() || MO.isImm())
181 if (MO.isReg() || MO.isImm())
194 if (MO.isReg() || MO.isImm())
206 if (MO.isReg() || MO.isImm())
|
| /external/llvm/lib/MC/ |
| MCInstrDesc.cpp | 47 if (MI.getOperand(i).isReg() &&
66 if (MI.getOperand(i).isReg() &&
|
| MCInst.cpp | 22 else if (isReg())
|
| /external/llvm/lib/Target/BPF/InstPrinter/ |
| BPFInstPrinter.cpp | 56 if (Op.isReg()) {
77 assert(RegOp.isReg() && "Register operand not a register");
|
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 56 bool isReg() const { return Kind == kRegister; }
64 assert(isReg() && "This is not a register operand!");
70 assert(isReg() && "This is not a register operand!");
|
| /external/llvm/lib/Target/Mips/ |
| MipsTargetStreamer.h | 84 const MCSymbol &Sym, bool IsReg);
199 const MCSymbol &Sym, bool IsReg) override;
252 const MCSymbol &Sym, bool IsReg) override;
|
| /sdk/find_java2/FindJava2/ |
| FindJava2.cpp | 120 bool isReg = (p == javaPath);
121 if (isReg) {
124 _tprintf(_T("%c [%s] %s\n"), isReg ? '*' : ' ', p.getVersion(), p.mPath);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitDouble.cpp | 113 assert(R.isReg());
169 if (MI->getOperand(1).isReg())
174 if (MI->getOperand(0).isReg())
201 if (!Op.isReg())
250 if (&MO == &Op || !MO.isReg() || MO.getSubReg())
410 if (Op.isReg() && Part.count(Op.getReg()))
467 assert(Cond[1].isReg() && "Unexpected Cond vector from AnalyzeBranch");
568 if (!Op.isReg()) {
673 assert(Op0.isReg() && Op1.isImm());
702 assert(Op0.isReg());
[all...] |
| HexagonGenMux.cpp | 132 if (!Mo->isReg() || Mo->isImplicit())
173 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
263 unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0;
264 unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0;
|
| /external/llvm/lib/Target/SystemZ/AsmParser/ |
| SystemZAsmParser.cpp | 196 bool isReg() const override {
199 bool isReg(RegisterKind RegKind) const {
310 bool isGR32() const { return isReg(GR32Reg); }
311 bool isGRH32() const { return isReg(GRH32Reg); }
313 bool isGR64() const { return isReg(GR64Reg); }
314 bool isGR128() const { return isReg(GR128Reg); }
315 bool isADDR32() const { return isReg(ADDR32Reg); }
316 bool isADDR64() const { return isReg(ADDR64Reg); }
318 bool isFP32() const { return isReg(FP32Reg); }
319 bool isFP64() const { return isReg(FP64Reg);
[all...] |
| /external/valgrind/VEX/useful/ |
| hd_fpu.c | 694 Bool isreg; local
727 IFDB(CC &t_addr), &isreg );
728 assert(!isreg);
827 IFDB(CC &t_addr), &isreg );
828 assert(!isreg);
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 54 assert(MI.getOperand(0).isReg());
61 return (MI.getNumOperands() > 0 && MI.getOperand(0).isReg()
84 assert(MI.getOperand(0).isReg());
|
