| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/rx/ |
| mvfc.sm | 0 mvfc {creg},{reg}
|
| mvfc.d | 9 0: fd 6a 00 mvfc psw, r0
10 3: fd 6a 0f mvfc psw, r15
11 6: fd 6a 30 mvfc fpsw, r0
12 9: fd 6a 3f mvfc fpsw, r15
13 c: fd 6a 20 mvfc usp, r0
14 f: fd 6a 2f mvfc usp, r15
15 12: fd 6a a0 mvfc isp, r0
16 15: fd 6a af mvfc isp, r15
17 18: fd 6a c0 mvfc intb, r0
18 1b: fd 6a cf mvfc intb, r1
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d10v/ |
| warning-001.s | 4 mvfc r0,cr6
|
| warning-003.s | 4 mvfc r0,cr12
|
| warning-005.s | 4 mvfc r0,cr13
|
| warning-007.s | 4 mvfc r0,cr13
|
| warning-008.s | 4 mvfc r0,cr15
|
| warning-010.s | 4 mvfc r0,cr4
|
| warning-012.s | 4 mvfc r0,cr5
|
| control-001.s | 4 mvfc r0,cr0
6 mvfc r0,cr1
8 mvfc r0,cr2
10 mvfc r0,cr3;
12 mvfc r0,cr7
14 mvfc r0,cr8
16 mvfc r0,cr9
18 mvfc r0,cr10
20 mvfc r0,cr11
22 mvfc r0,cr1
[all...] |
| control-001.d | 9 0: 69 00 56 00 mvfc r0, psw -> mvtc r0, psw
10 4: 69 01 56 20 mvfc r0, bpsw -> mvtc r0, bpsw
11 8: 69 02 56 40 mvfc r0, pc -> mvtc r0, pc
12 c: 69 03 56 60 mvfc r0, bpc -> mvtc r0, bpc
13 10: 69 07 56 e0 mvfc r0, rpt_c -> mvtc r0, rpt_c
14 14: 69 08 57 00 mvfc r0, rpt_s -> mvtc r0, rpt_s
15 18: 69 09 57 20 mvfc r0, rpt_e -> mvtc r0, rpt_e
16 1c: 69 0a 57 40 mvfc r0, mod_s -> mvtc r0, mod_s
17 20: 69 0b 57 60 mvfc r0, mod_e -> mvtc r0, mod_e
18 24: 69 0e 57 c0 mvfc r0, iba -> mvtc r0, ib
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m32r/ |
| uppercase.s | 5 mvfc R0,CBR
|
| uppercase.d | 10 0: 10 81 10 91 * mv r0,r1 -> mvfc r0,cbr
|
| allinsn.s | 342 .global mvfc
343 mvfc: label
344 mvfc fp,psw
|
| m32rx.s | 251 mvfc fp, cr1 || sub r2, fp
252 mvfc fp, cr1
|
| allinsn.d | 262 0+0150 <mvfc>:
263 150: 1d 90 f0 00 mvfc fp,psw \|\| nop
|
| m32rx.d | 160 e0: 1d 91 82 2d mvfc fp,cbr \|\| sub r2,fp
161 e4: 1d 91 02 2d mvfc fp,cbr -> sub r2,fp
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| m32r-desc.c | 910 /* mvfc $dr,$scr */
912 M32R_INSN_MVFC, "mvfc", "mvfc", 16,
[all...] |
| d10v-opc.c | 274 { "mvfc", SHORT_2, 1, MU, PAR, 0x5200, 0x7e01, { RDST, CSRC } },
|
| m32r-opc.c | 780 /* mvfc $dr,$scr */
[all...] |
| rx-decode.opc | 974 /** 1111 1101 0110 101s rsrc rdst mvfc %1, %0 */
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-d10v.c | 765 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
900 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */
[all...] |
| rx-parse.y | 158 %token MVFC MVTACHI MVTACLO MVTC MVTIPL
747 | MVFC CREG ',' REG
1038 OPC(MVFC),
[all...] |
| /toolchain/binutils/binutils-2.25/cpu/ |
| m32r.cpu | [all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/ |
| ChangeLog-2009 | 140 * gas/rx/mvfc.d: Remove expected uses of cpen register.
[all...] |
