/external/llvm/test/CodeGen/AMDGPU/ |
predicates.ll | 8 ; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel 26 ; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel 27 ; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel 53 ; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel 80 ; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel 81 ; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
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/external/llvm/lib/Target/AMDGPU/ |
R600ExpandSpecialInstrs.cpp | 90 AMDGPU::OpName::pred_sel); 92 AMDGPU::OpName::pred_sel); 93 // Copy the pred_sel bit
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EvergreenInstructions.td | 394 let pred_sel = 0; 442 LAST:$last, R600_Pred:$pred_sel, 444 " "#name#" $last OQAP, $src0$src0_rel $pred_sel", 464 LAST:$last, R600_Pred:$pred_sel, 466 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel", 497 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle), 498 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel",
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R600Packetizer.cpp | 192 // Does MII and MIJ share the same pred_sel ? 193 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel), 194 OpJ = TII->getOperandIdx(MIJ->getOpcode(), AMDGPU::OpName::pred_sel);
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R600InstrFormats.td | 75 bits<2> pred_sel; 90 let Word0{30-29} = pred_sel;
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R600InstrInfo.cpp | [all...] |
R600Instructions.td | 98 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 103 "$pred_sel $bank_swizzle"), 141 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 147 "$pred_sel $bank_swizzle"), 181 LAST:$last, R600_Pred:$pred_sel, LITERAL:$literal, 187 "$pred_sel" [all...] |
/external/mesa3d/src/gallium/drivers/r600/ |
r700_asm.c | 46 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) |
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r600_asm.h | 58 unsigned pred_sel; member in struct:r600_bytecode_alu
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r600_asm.c | 930 alu_prev->pred_sel == alu->pred_sel) { 940 alu_prev->pred_sel == alu->pred_sel) { [all...] |
r600_shader.c | 315 alu.pred_sel = bytes[bytes_read++]; 334 alu.pred_sel = 0; [all...] |