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    Searched full:rcond (Results 1 - 7 of 7) sorted by null

  /external/eigen/Eigen/src/SuperLUSupport/
SuperLUSupport.h 30 FLOATTYPE *rcond, FLOATTYPE *ferr, FLOATTYPE *berr, \
34 U, work, lwork, B, X, recip_pivot_growth, rcond, \
64 FLOATTYPE *rcond, \
68 U, work, lwork, B, X, recip_pivot_growth, rcond, \
617 RealScalar recip_pivot_growth, rcond; local
626 &recip_pivot_growth, &rcond,
667 RealScalar recip_pivot_growth, rcond; local
675 &recip_pivot_growth, &rcond,
932 RealScalar recip_pivot_growth, rcond; local
940 &recip_pivot_growth, &rcond,
976 RealScalar recip_pivot_growth, rcond; local
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  /external/llvm/lib/Target/Sparc/
SparcInstrFormats.td 280 class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins,
287 let Inst{12-10} = rcond;
293 class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins,
300 let Inst{12-10} = rcond;
SparcInstr64Bit.td 383 multiclass MOVR< bits<3> rcond, string OpcStr> {
384 def rr : F4_4r<0b101111, 0b00000, rcond, (outs I64Regs:$rd),
388 def ri : F4_4i<0b101111, rcond, (outs I64Regs:$rd),
401 multiclass FMOVR<bits<3> rcond, string OpcStr> {
403 def S : F4_4r<0b110101, 0b00101, rcond,
407 def D : F4_4r<0b110101, 0b00110, rcond,
411 def Q : F4_4r<0b110101, 0b00111, rcond,
  /toolchain/binutils/binutils-2.25/cpu/
xc16x.cpu 145 (dnf f-rcond "relative-cond" () 7 4) ;condition code required in JMPR
207 ; insn-rcond: bits 0-3
213 ; insn-rcond: bits 0-3
214 (define-normal-insn-enum insn-rcond "relative jump condition code op2 enums" () COND_ f-rcond
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  /toolchain/binutils/binutils-2.25/opcodes/
sparc-opc.c 120 #define RCOND(x) (((x) & 0x7) << 10) /* v9 */
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sparc-dis.c 176 unsigned int rcond:3;
xc16x-desc.c 671 { XC16X_F_RCOND, "f-rcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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