| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/rx/ |
| rotl.sm | 0 rotl #{uimm5},{reg}
2 rotl {reg},{reg}
|
| rotl.d | 9 0: fd 6e 00 rotl #0, r0
10 3: fd 6e 0f rotl #0, r15
11 6: fd 6f f0 rotl #31, r0
12 9: fd 6f ff rotl #31, r15
13 c: fd 66 00 rotl r0, r0
14 f: fd 66 0f rotl r0, r15
15 12: fd 66 f0 rotl r15, r0
16 15: fd 66 ff rotl r15, r15
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/h8300/ |
| rotsh.s | 3 rotl r0l
|
| rotshh.s | 4 rotl.b r0l
5 rotl.w r0
6 rotl.l er0
|
| rotshs.s | 4 rotl.b r0l
5 rotl.b #2,r0l
6 rotl.w r0
7 rotl.w #2,r0
8 rotl.l er0
9 rotl.l #2,er0
|
| t11_logs.s | [all...] |
| ffxx1-coff.s | 18 rotl r0l
|
| ffxx1-elf.s | 18 rotl r0l
|
| ffxx1-coff.d | 20 0+0416 <.*>.*rotl.b r0l
|
| ffxx1-elf.d | 20 0+0416 <.*>.*rotl.b r0l
|
| /external/llvm/test/TableGen/ |
| SetTheory.td | 96 // The 'rotl' operator rotates left, but also accepts a negative shift.
97 def rotl;
98 def S6a : Set<(rotl S0f, 0)>;
99 def S6b : Set<(rotl S0f, 1)>;
100 def S6c : Set<(rotl S0f, 3)>;
101 def S6d : Set<(rotl S0f, 4)>;
102 def S6e : Set<(rotl S0f, 5)>;
103 def S6f : Set<(rotl S0f, -1)>;
104 def S6g : Set<(rotl S0f, -4)>;
105 def S6h : Set<(rotl S0f, -5)>
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| rotate.ll | 4 ;; select ROTL. Make sure if generates the basic ushr/shl.
|
| /external/llvm/test/CodeGen/ARM/ |
| rotate.ll | 4 ;; select ROTL. Make sure if generates the basic VSHL/VSHR.
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips32r2.s | 35 rotl $25, $10, 4
37 rotl $25, $10, $4
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.td | 131 let AltOrders = [(rotl GPR32common, 8)];
136 let AltOrders = [(rotl GPR64common, 8)];
141 let AltOrders = [(rotl GPR32, 8)];
145 let AltOrders = [(rotl GPR64, 8)];
151 let AltOrders = [(rotl GPR32sp, 8)];
155 let AltOrders = [(rotl GPR64sp, 8)];
414 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
416 [(rotl FPR64, 0), (rotl FPR64, 1)
[all...] |
| /external/llvm/test/CodeGen/SystemZ/ |
| risbg-01.ll | 143 %rotl = or i32 %parta, %partb
144 %and = and i32 %rotl, 248
155 %rotl = or i64 %parta, %partb
156 %and = and i64 %rotl, 248
167 %rotl = or i32 %parta, %partb
168 %and = and i32 %rotl, 114688
179 %rotl = or i64 %parta, %partb
180 %and = and i64 %rotl, 114688
193 %rotl = or i32 %parta, %partb
194 %and = and i32 %rotl, 12
[all...] |
| /prebuilts/go/darwin-x86/src/runtime/ |
| hash32.go | 84 // Note: in order to get the compiler to issue rotl instructions, we
86 // TODO: convince the compiler to issue rotl instructions after inlining.
|
| hash64.go | 84 // Note: in order to get the compiler to issue rotl instructions, we
86 // TODO: convince the compiler to issue rotl instructions after inlining.
|
| /prebuilts/go/linux-x86/src/runtime/ |
| hash32.go | 84 // Note: in order to get the compiler to issue rotl instructions, we
86 // TODO: convince the compiler to issue rotl instructions after inlining.
|
| hash64.go | 84 // Note: in order to get the compiler to issue rotl instructions, we
86 // TODO: convince the compiler to issue rotl instructions after inlining.
|
| /external/llvm/lib/Target/X86/ |
| X86InstrShiftRotate.td | 473 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
476 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize16;
479 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize32;
482 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
487 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
490 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
494 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
499 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
505 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))],
509 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.td | 276 (decimate (rotl SPR, 1), 4),
277 (decimate (rotl SPR, 1), 2))];
295 let AltOrders = [(rotl DPR, 16),
296 (add (decimate (rotl DPR, 16), 2), (rotl DPR, 16))];
316 let AltOrders = [(rotl QPR, 8)];
342 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
377 let AltOrders = [(rotl QQPR, 8)];
400 let AltOrders = [(rotl QQQQPR, 8)]
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.h | 46 /// LowerROTL - Lower ROTL opcode to BITALIGN
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tilegx/ |
| t_insns.s | 227 { blbc r15, target ; rotl r5, r6, r7 }
308 { add r15, r16, r17 ; prefetch_l2 r25 ; rotl r5, r6, r7 }
347 { add r5, r6, r7 ; ld1u r25, r26 ; rotl r15, r16, r17 }
417 { addi r15, r16, 5 ; prefetch_l2 r25 ; rotl r5, r6, r7 }
456 { addi r5, r6, 5 ; ld1u r25, r26 ; rotl r15, r16, r17 }
[all...] |
| /external/boringssl/src/crypto/md5/asm/ |
| md5-586.pl | 64 &rotl($a,$s);
89 &rotl($a,$s);
112 &rotl($a,$s);
135 &rotl($a,$s);
161 &rotl($a,$s);
|
