| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 542 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0);
543 if (ShiftOp && !ShiftOp->isShift())
544 ShiftOp = nullptr;
546 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) {
560 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1));
565 Value *X = ShiftOp->getOperand(0);
570 if (I.getOpcode() == ShiftOp->getOpcode()) {
587 ShiftOp->getOpcode() == Instruction::Shl)
[all...] |
| /prebuilts/go/darwin-x86/test/fixedbugs/ |
| issue9604b.go | 109 type shiftop struct { type
114 var shiftops = []shiftop{
115 shiftop{"<<", func(x *big.Int, i uint) *big.Int { return new(big.Int).Lsh(x, i) }},
116 shiftop{">>", func(x *big.Int, i uint) *big.Int { return new(big.Int).Rsh(x, i) }},
|
| /prebuilts/go/linux-x86/test/fixedbugs/ |
| issue9604b.go | 109 type shiftop struct { type
114 var shiftops = []shiftop{
115 shiftop{"<<", func(x *big.Int, i uint) *big.Int { return new(big.Int).Lsh(x, i) }},
116 shiftop{">>", func(x *big.Int, i uint) *big.Int { return new(big.Int).Rsh(x, i) }},
|
| /external/v8/src/arm/ |
| constants-arm.h | 240 enum ShiftOp {
247 // Use a special code to make the distinction. The RRX ShiftOp is only used
570 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); }
571 inline ShiftOp ShiftField() const {
572 return static_cast<ShiftOp>(BitField(6, 5));
|
| assembler-arm.h | 464 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
478 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
504 ShiftOp shift_op() const { return shift_op_; }
509 ShiftOp shift_op_;
537 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
567 ShiftOp shift_op_;
[all...] |
| assembler-arm.cc | 277 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
298 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
332 ShiftOp shift_op, int shift_imm, AddrMode am) {
[all...] |
| disasm-arm.cc | 190 ShiftOp shift = instr->ShiftField();
[all...] |
| simulator-arm.cc | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 713 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
714 bool isASR = (ShiftOp & (1 << 5)) != 0;
715 unsigned Amt = ShiftOp & 0x1f;
[all...] |
| /external/doclava/src/com/google/doclava/parser/ |
| Java.g | 1034 (shiftOp additiveExpression
1039 shiftOp
[all...] |
| JavaParser.java | 374 "synpred229_Java", "synpred170_Java", "shiftOp", "synpred134_Java",
[all...] |
| /external/libgdx/gdx/jni/gdx2d/ |
| stb_image.h | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrFormats.td | 606 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
610 let MIOperandInfo = (ops regclass, shiftop);
[all...] |
