HomeSort by relevance Sort by last modified time
    Searched full:shld (Results 1 - 25 of 121) sorted by null

1 2 3 4 5

  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
inval-reg.s 10 shld $0x90, %bx,%ecx label
11 shld %cl, %bx,%ecx label
12 shld %bx,%ecx label
inval-reg.l 63 [ ]*10[ ]+shld \$0x90, %bx,%ecx
64 [ ]*11[ ]+shld %cl, %bx,%ecx
65 [ ]*12[ ]+shld %bx,%ecx
intel.s 339 shld 0x90909090[eax], edx, 0x90
340 shld 0x90909090[eax], edx, cl
554 shld 0x90909090[eax], dx, 0x90
555 shld 0x90909090[eax], dx, cl
633 shld eax, edx, cl
opcode.s 336 shld $0x90,%edx,0x90909090(%eax)
337 shld %cl,%edx,0x90909090(%eax)
549 shld $0x90,%dx,0x90909090(%eax)
550 shld %cl,%dx,0x90909090(%eax)
582 shld %cl,%edx,%eax
  /external/llvm/test/CodeGen/X86/
2006-01-19-ISelFoldingBug.ll 2 ; RUN: grep shld | count 1
4 ; Check that the isel does not fold the shld, which already folds a load
shift-coalesce.ll 2 ; RUN: grep "shld.*cl"
x86-64-double-shifts-Oz-Os-O2.ll 4 ; Verify that we generate shld insruction when we are optimizing for size,
26 ; Verify that we generate shld insruction when we are optimizing for size,
47 ; Verify that we do not generate shld insruction when we are not optimizing
x86-64-double-shifts-var.ll 20 ; double precision shift instructions we do not generate 'shld' or 'shrd'
30 ; CHECK-NOT: shld
x86-64-double-precision-shift-left.ll 4 ; of instructions with lower latencies instead of shld instruction.
rot64.ll 4 ; RUN: grep shld %t | count 2
  /external/boringssl/win-x86/crypto/sha/
sha1-586.asm     [all...]
  /external/boringssl/win-x86_64/crypto/sha/
sha1-x86_64.asm     [all...]
  /external/boringssl/src/crypto/curve25519/asm/
x25519-asm-x86_64.S 265 shld $13,%r8,%r9 label
267 shld $13,%r10,%r11 label
270 shld $13,%r12,%r13 label
273 shld $13,%r14,%r15 label
276 shld $13,%rbx,%rbp label
407 shld $13,%rcx,%r8 label
409 shld $13,%r9,%r10 label
412 shld $13,%r11,%r12 label
415 shld $13,%r13,%r14 label
418 shld $13,%r15,%rb label
584 shld $13,%rsi,%rcx label
586 shld $13,%r8,%r9 label
589 shld $13,%r10,%r11 label
592 shld $13,%r12,%r13 label
595 shld $13,%r14,%r15 label
699 shld $13,%rsi,%rcx label
701 shld $13,%r8,%r9 label
704 shld $13,%r10,%r11 label
707 shld $13,%r12,%r13 label
710 shld $13,%r14,%r15 label
904 shld $13,%rsi,%rcx label
906 shld $13,%r8,%r9 label
909 shld $13,%r10,%r11 label
912 shld $13,%r12,%r13 label
915 shld $13,%r14,%r15 label
1054 shld $13,%rsi,%rcx label
1056 shld $13,%r8,%r9 label
1059 shld $13,%r10,%r11 label
1062 shld $13,%r12,%r13 label
1065 shld $13,%r14,%r15 label
1194 shld $13,%rsi,%rcx label
1196 shld $13,%r8,%r9 label
1199 shld $13,%r10,%r11 label
1202 shld $13,%r12,%r13 label
1205 shld $13,%r14,%r15 label
1309 shld $13,%rsi,%rcx label
1311 shld $13,%r8,%r9 label
1314 shld $13,%r10,%r11 label
1317 shld $13,%r12,%r13 label
1320 shld $13,%r14,%r15 label
1459 shld $13,%rsi,%rcx label
1461 shld $13,%r8,%r9 label
1464 shld $13,%r10,%r11 label
1467 shld $13,%r12,%r13 label
1470 shld $13,%r14,%r15 label
1609 shld $13,%rsi,%rcx label
1611 shld $13,%r8,%r9 label
1614 shld $13,%r10,%r11 label
1617 shld $13,%r12,%r13 label
1620 shld $13,%r14,%r15 label
1795 shld $13,%rsi,%rcx label
1797 shld $13,%r8,%r9 label
1800 shld $13,%r10,%r11 label
1803 shld $13,%r12,%r13 label
1806 shld $13,%r14,%r15 label
    [all...]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/
sh2a.s 92 shld r3,r4
sh2a.d 66 0x000000a8 44 3d shld r3,r4
  /external/boringssl/src/crypto/bn/asm/
rsaz-x86_64.pl 192 adcq %r9, %r9 #shld \$1, %r8, %r9
253 lea (%rcx,%r10,2), %r10 #shld \$1, %rcx, %r10
255 adcq %r11, %r11 #shld \$1, %r10, %r11
293 lea (%rbx,%r12,2), %r12 #shld \$1, %rbx, %r12
311 leaq (%r10,%r13,2), %r13 #shld \$1, %r12, %r13
341 leaq (%rcx,%r14,2), %r14 #shld \$1, %rcx, %r14
359 leaq (%r12,%r15,2),%r15 #shld \$1, %r14, %r15
384 leaq (%rbx,%r8,2), %r8 #shld \$1, %rbx, %r8
399 leaq (%r12,%r9,2), %r9 #shld \$1, %r8, %r9
423 leaq (%rcx,%r10,2), %r10 #shld \$1, %rcx, %r1
    [all...]
  /external/llvm/lib/Target/X86/
X86InstrShiftRotate.td     [all...]
  /external/llvm/test/MC/X86/
intel-syntax.s 377 shld DX, BX label
378 shld DX, BX, CL label
379 shld DX, BX, 1 label
380 shld [RAX], BX label
381 shld [RAX], BX, CL label
  /external/v8/test/cctest/
test-disasm-x87.cc 122 __ shld(edx, ecx);
217 __ shld(edx, Operand(ebx, ecx, times_4, 10000));
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/arch/
sh2a-nofpu-or-sh3-nommu.s 16 shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
sh2a-nofpu-or-sh4-nommu-nofpu.s 126 shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
sh2a-or-sh3e.s 130 shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
sh3-nommu.s 137 shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
sh3.s 132 shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
sh3e.s 136 shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}

Completed in 1072 milliseconds

1 2 3 4 5