| /external/llvm/test/CodeGen/AArch64/ |
| neon-diagnostics.ll | 16 ; CHECK-NOT: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #35
|
| arm64-vecFold.ll | 10 ; CHECK-NEXT: shrn2.16b v0, v1, #5
26 ; CHECK-NEXT: shrn2.8h v0, v1, #5
42 ; CHECK-NEXT: shrn2.4s v0, v1, #5
71 ; CHECK-NEXT: shrn2.8h v0, v2, #5
|
| arm64-neon-simd-shift.ll | 263 ; CHECK: shrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
275 ; CHECK: shrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
287 ; CHECK: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
299 ; CHECK: shrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
311 ; CHECK: shrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
323 ; CHECK: shrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
|
| arm64-vshift.ll | 706 ;CHECK: shrn2.16b v0, {{v[0-9]+}}, #1
717 ;CHECK: shrn2.8h v0, {{v[0-9]+}}, #1
728 ;CHECK: shrn2.4s v0, {{v[0-9]+}}, #1
[all...] |
| /external/clang/test/CodeGen/ |
| arm64_neon_high_half.c | 257 // CHECK: shrn2.4s
277 // CHECK: shrn2.16b
282 // CHECK: shrn2.8h
287 // CHECK: shrn2.4s
292 // CHECK: shrn2.16b
297 // CHECK: shrn2.8h
302 // CHECK: shrn2.4s
|
| aarch64-neon-intrinsics.c | [all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-simd-shift.s | 265 shrn2 v0.16b, v1.8h, #3
266 shrn2 v0.8h, v1.4s, #3
267 shrn2 v0.4s, v1.2d, #3
272 // CHECK: shrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x84,0x0d,0x4f]
273 // CHECK: shrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x84,0x1d,0x4f]
274 // CHECK: shrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x84,0x3d,0x4f]
|
| arm64-advsimd.s | [all...] |
| neon-diagnostics.s | [all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_3DLUT.S | 90 shrn2 v14.8h, v9.4s, #8
|
| rsCpuIntrinsics_advsimd_Convolve.S | 86 shrn2 v8.8h, v9.4s, #8
|
| rsCpuIntrinsics_advsimd_Resize.S | 436 shrn2 v1.8h, v13.4s, #1
445 shrn2 v2.8h, v13.4s, #1
|
| /external/libavc/common/armv8/ |
| ih264_resi_trans_quant_av8.s | 568 shrn2 v0.8h, v23.4s, #1 //i4_value = (x3 + x2) >> 1;
570 shrn2 v1.8h, v25.4s, #1 //i4_value = (x3 - x2) >> 1;
|
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| scale_neon64.cc | 630 "shrn2 v6.8h, v17.4s, #16 \n"
[all...] |
| /external/vixl/src/vixl/a64/ |
| logic-a64.cc | 2507 LogicVRegister Simulator::shrn2(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| macro-assembler-a64.h | [all...] |
| simulator-a64.h | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | [all...] |
| /external/vixl/test/ |
| test-simulator-a64.cc | [all...] |
| test-simulator-traces-a64.h | [all...] |
| /external/libyuv/files/source/ |
| scale_neon64.cc | [all...] |
| row_neon64.cc | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-dis-2.c | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
