Lines Matching defs:out
244 Location out = locations->Out();
245 if (out.IsValid()) {
246 DCHECK(out.IsRegister() && !locations->GetLiveRegisters()->ContainsCoreRegister(out.reg()));
248 mips_codegen->MoveLocation(out, calling_convention.GetReturnLocation(type), type);
280 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg()));
296 mips_codegen->MoveLocation(locations->Out(),
383 Location object_class = instruction_->IsCheckCast() ? locations->GetTemp(0) : locations->Out();
386 || !locations->GetLiveRegisters()->ContainsCoreRegister(locations->Out().reg()));
412 mips_codegen->MoveLocation(locations->Out(), ret_loc, ret_type);
1190 Register dst = locations->Out().AsRegister<Register>();
1234 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
1235 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
1376 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
1441 Register dst = locations->Out().AsRegister<Register>();
1477 // when `rhs_reg & 31 == 0` is OK even though we don't shift `lhs` left all the way out
1490 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
1491 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
1496 codegen_->Move64(locations->Out(), locations->InAt(0));
1673 Register out = locations->Out().AsRegister<Register>();
1677 __ LoadFromOffset(kLoadUnsignedByte, out, obj, offset);
1680 __ LoadFromOffset(kLoadUnsignedByte, out
1687 Register out = locations->Out().AsRegister<Register>();
1691 __ LoadFromOffset(kLoadSignedByte, out, obj, offset);
1694 __ LoadFromOffset(kLoadSignedByte, out, TMP, data_offset);
1701 Register out = locations->Out().AsRegister<Register>();
1705 __ LoadFromOffset(kLoadSignedHalfword, out, obj, offset);
1709 __ LoadFromOffset(kLoadSignedHalfword, out, TMP, data_offset);
1716 Register out = locations->Out().AsRegister<Register>();
1720 __ LoadFromOffset(kLoadUnsignedHalfword, out, obj, offset);
1724 __ LoadFromOffset(kLoadUnsignedHalfword, out, TMP, data_offset);
1733 Register out = locations->Out().AsRegister<Register>();
1737 __ LoadFromOffset(kLoadWord, out, obj, offset);
1741 __ LoadFromOffset(kLoadWord, out, TMP, data_offset);
1748 Register out = locations->Out().AsRegisterPairLow<Register>();
1752 __ LoadFromOffset(kLoadDoubleword, out, obj, offset);
1756 __ LoadFromOffset(kLoadDoubleword, out, TMP, data_offset);
1763 FRegister out = locations->Out().AsFpuRegister<FRegister>();
1767 __ LoadSFromOffset(out, obj, offset);
1771 __ LoadSFromOffset(out, TMP, data_offset);
1778 FRegister out = locations->Out().AsFpuRegister<FRegister>();
1782 __ LoadDFromOffset(out, obj, offset);
1786 __ LoadDFromOffset(out, TMP, data_offset);
1808 Register out = locations->Out().AsRegister<Register>();
1809 __ LoadFromOffset(kLoadWord, out, obj, offset);
2073 Register res = locations->Out().AsRegister<Register>();
2224 Register dst = locations->Out().AsRegister<Register>();
2270 Register out = locations->Out().AsRegister<Register>();
2276 __ Move(out, ZERO);
2279 __ Subu(out, ZERO, dividend);
2280 } else if (out != dividend) {
2281 __ Move(out, dividend);
2294 Register out = locations->Out().AsRegister<Register>();
2308 __ Addu(out, dividend, TMP);
2309 __ Sra(out, out, ctz_imm);
2311 __ Subu(out, ZERO, out);
2317 __ Subu(out, dividend, TMP);
2318 __ Andi(out, out, 1);
2319 __ Addu(out, out, TMP);
2323 __ Addu(out, dividend, TMP);
2325 __ Andi(out, out, abs_imm - 1);
2327 __ Sll(out, out, 32 - ctz_imm);
2328 __ Srl(out, out, 32 - ctz_imm);
2330 __ Subu(out, out, TMP);
2343 Register out = locations->Out().AsRegister<Register>();
2371 __ Sra(out, TMP, 31);
2372 __ Subu(out, TMP, out);
2382 __ Subu(out, dividend, TMP);
2391 Register out = locations->Out().AsRegister<Register>();
2412 __ DivR6(out, dividend, divisor);
2414 __ DivR2(out, dividend, divisor);
2418 __ ModR6(out, dividend, divisor);
2420 __ ModR2(out, dividend, divisor);
2482 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
2620 Register dst = locations->Out().AsRegister<Register>();
3371 codegen_->MoveLocation(locations->Out(), locations->InAt(1), select->GetType());
3469 locations->Out().AsFpuRegister<FRegister>());
3471 locations->Out().AsFpuRegister<FRegister>());
3477 DCHECK(locations->Out().IsRegisterPair());
3478 dst = locations->Out().AsRegisterPairLow<Register>();
3479 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
3490 DCHECK(locations->Out().IsRegister());
3491 dst = locations->Out().AsRegister<Register>();
3495 DCHECK(locations->Out().IsFpuRegister());
3496 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
3673 Register out = locations->Out().AsRegister<Register>();
3679 __ Move(out, ZERO);
3683 __ LoadFromOffset(kLoadWord, out, obj, mirror::Object::ClassOffset().Int32Value());
3686 __ Xor(out, out, cls);
3687 __ Sltiu(out, out, 1);
3693 __ Bne(out, cls, slow_path->GetEntryLabel());
3694 __ LoadConst32(out, 1);
3854 // Currently filtered out by GetSupportedInvokeStaticOrDirectDispatch().
3901 // Currently filtered out by GetSupportedInvokeStaticOrDirectDispatch().
3989 Register out = locations->Out().AsRegister<Register>();
3994 __ LoadFromOffset(kLoadWord, out, current_method,
3997 __ LoadFromOffset(kLoadWord, out, current_method,
3999 __ LoadFromOffset(kLoadWord, out, out, CodeGenerator::GetCacheOffset(cls->GetTypeIndex()));
4010 __ Beqz(out, slow_path->GetEntryLabel());
4013 GenerateClassInitializationCheck(slow_path, out);
4032 Register out = load->GetLocations()->Out().AsRegister<Register>();
4033 __ LoadFromOffset(kLoadWord, out, TR, GetExceptionTlsOffset());
4055 Register out = locations->Out().AsRegister<Register>();
4057 __ LoadFromOffset(kLoadWord, out, current_method, ArtMethod::DeclaringClassOffset().Int32Value());
4058 __ LoadFromOffset(kLoadWord, out, out, mirror::Class::DexCacheStringsOffset().Int32Value());
4059 __ LoadFromOffset(kLoadWord, out, out, CodeGenerator::GetCacheOffset(load->GetStringIndex()));
4064 __ Beqz(out, slow_path->GetEntryLabel());
4133 Register dst = locations->Out().AsRegister<Register>();
4145 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4146 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
4183 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4225 Register dst = locations->Out().AsRegister<Register>();
4231 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4232 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
4243 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4329 Register dst = locations->Out().AsRegister<Register>();
4336 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4337 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
4358 __ Xori(locations->Out().AsRegister<Register>(),
4764 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4765 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
4771 Register dst = locations->Out().AsRegister<Register>();
4811 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4837 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4852 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4853 Register dst_low = locations->Out().AsRegisterPairLow<Register>();
4934 Register dst = locations->Out().AsRegister<Register>();
5009 FRegister dst = locations->Out().AsFpuRegister<FRegister>();
5196 locations->Out().AsRegister<Register>(),
5203 locations->Out().AsRegister<Register>(),
5207 locations->Out().AsRegister<Register>(),
5208 locations->Out().AsRegister<Register>(),
