Lines Matching refs:CpuRegister
27 std::ostream& operator<<(std::ostream& os, const CpuRegister& reg) {
39 void X86_64Assembler::call(CpuRegister reg) {
63 void X86_64Assembler::pushq(CpuRegister reg) {
91 void X86_64Assembler::popq(CpuRegister reg) {
106 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) {
122 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) {
141 void X86_64Assembler::movq(CpuRegister dst, CpuRegister src) {
150 void X86_64Assembler::movl(CpuRegister dst, CpuRegister src) {
158 void X86_64Assembler::movq(CpuRegister dst, const Address& src) {
166 void X86_64Assembler::movl(CpuRegister dst, const Address& src) {
174 void X86_64Assembler::movq(const Address& dst, CpuRegister src) {
182 void X86_64Assembler::movl(const Address& dst, CpuRegister src) {
197 void X86_64Assembler::movntl(const Address& dst, CpuRegister src) {
205 void X86_64Assembler::movntq(const Address& dst, CpuRegister src) {
213 void X86_64Assembler::cmov(Condition c, CpuRegister dst, CpuRegister src) {
217 void X86_64Assembler::cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit) {
226 void X86_64Assembler::cmov(Condition c, CpuRegister dst, const Address& src, bool is64bit) {
239 void X86_64Assembler::movzxb(CpuRegister dst, CpuRegister src) {
248 void X86_64Assembler::movzxb(CpuRegister dst, const Address& src) {
259 void X86_64Assembler::movsxb(CpuRegister dst, CpuRegister src) {
268 void X86_64Assembler::movsxb(CpuRegister dst, const Address& src) {
279 void X86_64Assembler::movb(CpuRegister /*dst*/, const Address& /*src*/) {
284 void X86_64Assembler::movb(const Address& dst, CpuRegister src) {
302 void X86_64Assembler::movzxw(CpuRegister dst, CpuRegister src) {
311 void X86_64Assembler::movzxw(CpuRegister dst, const Address& src) {
320 void X86_64Assembler::movsxw(CpuRegister dst, CpuRegister src) {
329 void X86_64Assembler::movsxw(CpuRegister dst, const Address& src) {
338 void X86_64Assembler::movw(CpuRegister /*dst*/, const Address& /*src*/) {
343 void X86_64Assembler::movw(const Address& dst, CpuRegister src) {
364 void X86_64Assembler::leaq(CpuRegister dst, const Address& src) {
372 void X86_64Assembler::leal(CpuRegister dst, const Address& src) {
419 void X86_64Assembler::movsxd(CpuRegister dst, CpuRegister src) {
427 void X86_64Assembler::movsxd(CpuRegister dst, const Address& src) {
435 void X86_64Assembler::movd(XmmRegister dst, CpuRegister src) {
439 void X86_64Assembler::movd(CpuRegister dst, XmmRegister src) {
443 void X86_64Assembler::movd(XmmRegister dst, CpuRegister src, bool is64bit) {
452 void X86_64Assembler::movd(CpuRegister dst, XmmRegister src, bool is64bit) {
673 void X86_64Assembler::cvtsi2ss(XmmRegister dst, CpuRegister src) {
678 void X86_64Assembler::cvtsi2ss(XmmRegister dst, CpuRegister src, bool is64bit) {
708 void X86_64Assembler::cvtsi2sd(XmmRegister dst, CpuRegister src) {
713 void X86_64Assembler::cvtsi2sd(XmmRegister dst, CpuRegister src, bool is64bit) {
743 void X86_64Assembler::cvtss2si(CpuRegister dst, XmmRegister src) {
773 void X86_64Assembler::cvtsd2si(CpuRegister dst, XmmRegister src) {
783 void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src) {
788 void X86_64Assembler::cvttss2si(CpuRegister dst, XmmRegister src, bool is64bit) {
803 void X86_64Assembler::cvttsd2si(CpuRegister dst, XmmRegister src) {
808 void X86_64Assembler::cvttsd2si(CpuRegister dst, XmmRegister src, bool is64bit) {
1174 void X86_64Assembler::xchgl(CpuRegister dst, CpuRegister src) {
1177 // It's a bit awkward, as CpuRegister has a const field, so assignment and thus swapping doesn't
1194 void X86_64Assembler::xchgq(CpuRegister dst, CpuRegister src) {
1197 // It's a bit awkward, as CpuRegister has a const field, so assignment and thus swapping doesn't
1219 void X86_64Assembler::xchgl(CpuRegister reg, const Address& address) {
1236 void X86_64Assembler::cmpl(CpuRegister reg, const Immediate& imm) {
1244 void X86_64Assembler::cmpl(CpuRegister reg0, CpuRegister reg1) {
1252 void X86_64Assembler::cmpl(CpuRegister reg, const Address& address) {
1260 void X86_64Assembler::cmpl(const Address& address, CpuRegister reg) {
1276 void X86_64Assembler::cmpq(CpuRegister reg0, CpuRegister reg1) {
1284 void X86_64Assembler::cmpq(CpuRegister reg, const Immediate& imm) {
1292 void X86_64Assembler::cmpq(CpuRegister reg, const Address& address) {
1308 void X86_64Assembler::addl(CpuRegister dst, CpuRegister src) {
1316 void X86_64Assembler::addl(CpuRegister reg, const Address& address) {
1324 void X86_64Assembler::testl(CpuRegister reg1, CpuRegister reg2) {
1332 void X86_64Assembler::testl(CpuRegister reg, const Address& address) {
1340 void X86_64Assembler::testl(CpuRegister reg, const Immediate& immediate) {
1343 // we only test the byte CpuRegister to keep the encoding short.
1366 void X86_64Assembler::testq(CpuRegister reg1, CpuRegister reg2) {
1374 void X86_64Assembler::testq(CpuRegister reg, const Address& address) {
1382 void X86_64Assembler::andl(CpuRegister dst, CpuRegister src) {
1390 void X86_64Assembler::andl(CpuRegister reg, const Address& address) {
1398 void X86_64Assembler::andl(CpuRegister dst, const Immediate& imm) {
1405 void X86_64Assembler::andq(CpuRegister reg, const Immediate& imm) {
1413 void X86_64Assembler::andq(CpuRegister dst, CpuRegister src) {
1421 void X86_64Assembler::andq(CpuRegister dst, const Address& src) {
1429 void X86_64Assembler::orl(CpuRegister dst, CpuRegister src) {
1437 void X86_64Assembler::orl(CpuRegister reg, const Address& address) {
1445 void X86_64Assembler::orl(CpuRegister dst, const Immediate& imm) {
1452 void X86_64Assembler::orq(CpuRegister dst, const Immediate& imm) {
1460 void X86_64Assembler::orq(CpuRegister dst, CpuRegister src) {
1468 void X86_64Assembler::orq(CpuRegister dst, const Address& src) {
1476 void X86_64Assembler::xorl(CpuRegister dst, CpuRegister src) {
1484 void X86_64Assembler::xorl(CpuRegister reg, const Address& address) {
1492 void X86_64Assembler::xorl(CpuRegister dst, const Immediate& imm) {
1499 void X86_64Assembler::xorq(CpuRegister dst, CpuRegister src) {
1507 void X86_64Assembler::xorq(CpuRegister dst, const Immediate& imm) {
1514 void X86_64Assembler::xorq(CpuRegister dst, const Address& src) {
1575 void X86_64Assembler::addl(CpuRegister reg, const Immediate& imm) {
1582 void X86_64Assembler::addq(CpuRegister reg, const Immediate& imm) {
1590 void X86_64Assembler::addq(CpuRegister dst, const Address& address) {
1598 void X86_64Assembler::addq(CpuRegister dst, CpuRegister src) {
1607 void X86_64Assembler::addl(const Address& address, CpuRegister reg) {
1622 void X86_64Assembler::subl(CpuRegister dst, CpuRegister src) {
1630 void X86_64Assembler::subl(CpuRegister reg, const Immediate& imm) {
1637 void X86_64Assembler::subq(CpuRegister reg, const Immediate& imm) {
1645 void X86_64Assembler::subq(CpuRegister dst, CpuRegister src) {
1653 void X86_64Assembler::subq(CpuRegister reg, const Address& address) {
1661 void X86_64Assembler::subl(CpuRegister reg, const Address& address) {
1682 void X86_64Assembler::idivl(CpuRegister reg) {
1690 void X86_64Assembler::idivq(CpuRegister reg) {
1698 void X86_64Assembler::imull(CpuRegister dst, CpuRegister src) {
1706 void X86_64Assembler::imull(CpuRegister dst, CpuRegister src, const Immediate& imm) {
1728 void X86_64Assembler::imull(CpuRegister reg, const Immediate& imm) {
1733 void X86_64Assembler::imull(CpuRegister reg, const Address& address) {
1742 void X86_64Assembler::imulq(CpuRegister dst, CpuRegister src) {
1751 void X86_64Assembler::imulq(CpuRegister reg, const Immediate& imm) {
1755 void X86_64Assembler::imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm) {
1776 void X86_64Assembler::imulq(CpuRegister reg, const Address& address) {
1785 void X86_64Assembler::imull(CpuRegister reg) {
1793 void X86_64Assembler::imulq(CpuRegister reg) {
1809 void X86_64Assembler::mull(CpuRegister reg) {
1825 void X86_64Assembler::shll(CpuRegister reg, const Immediate& imm) {
1830 void X86_64Assembler::shlq(CpuRegister reg, const Immediate& imm) {
1835 void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) {
1840 void X86_64Assembler::shlq(CpuRegister operand, CpuRegister shifter) {
1845 void X86_64Assembler::shrl(CpuRegister reg, const Immediate& imm) {
1850 void X86_64Assembler::shrq(CpuRegister reg, const Immediate& imm) {
1855 void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) {
1860 void X86_64Assembler::shrq(CpuRegister operand, CpuRegister shifter) {
1865 void X86_64Assembler::sarl(CpuRegister reg, const Immediate& imm) {
1870 void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) {
1875 void X86_64Assembler::sarq(CpuRegister reg, const Immediate& imm) {
1880 void X86_64Assembler::sarq(CpuRegisterCpuRegister shifter) {
1885 void X86_64Assembler::roll(CpuRegister reg, const Immediate& imm) {
1890 void X86_64Assembler::roll(CpuRegister operand, CpuRegister shifter) {
1895 void X86_64Assembler::rorl(CpuRegister reg, const Immediate& imm) {
1900 void X86_64Assembler::rorl(CpuRegister operand, CpuRegister shifter) {
1905 void X86_64Assembler::rolq(CpuRegister reg, const Immediate& imm) {
1910 void X86_64Assembler::rolq(CpuRegister operand, CpuRegister shifter) {
1915 void X86_64Assembler::rorq(CpuRegister reg, const Immediate& imm) {
1920 void X86_64Assembler::rorq(CpuRegister operand, CpuRegister shifter) {
1925 void X86_64Assembler::negl(CpuRegister reg) {
1933 void X86_64Assembler::negq(CpuRegister reg) {
1941 void X86_64Assembler::notl(CpuRegister reg) {
1949 void X86_64Assembler::notq(CpuRegister reg) {
2062 void X86_64Assembler::jmp(CpuRegister reg) {
2128 void X86_64Assembler::cmpxchgl(const Address& address, CpuRegister reg) {
2137 void X86_64Assembler::cmpxchgq(const Address& address, CpuRegister reg) {
2162 void X86_64Assembler::AddImmediate(CpuRegister reg, const Immediate& imm) {
2174 void X86_64Assembler::setcc(Condition condition, CpuRegister dst) {
2185 void X86_64Assembler::bswapl(CpuRegister dst) {
2192 void X86_64Assembler::bswapq(CpuRegister dst) {
2199 void X86_64Assembler::bsfl(CpuRegister dst, CpuRegister src) {
2207 void X86_64Assembler::bsfl(CpuRegister dst, const Address& src) {
2215 void X86_64Assembler::bsfq(CpuRegister dst, CpuRegister src) {
2223 void X86_64Assembler::bsfq(CpuRegister dst, const Address& src) {
2231 void X86_64Assembler::bsrl(CpuRegister dst, CpuRegister src) {
2239 void X86_64Assembler::bsrl(CpuRegister dst, const Address& src) {
2247 void X86_64Assembler::bsrq(CpuRegister dst, CpuRegister src) {
2255 void X86_64Assembler::bsrq(CpuRegister dst, const Address& src) {
2263 void X86_64Assembler::popcntl(CpuRegister dst, CpuRegister src) {
2272 void X86_64Assembler::popcntl(CpuRegister dst, const Address& src) {
2281 void X86_64Assembler::popcntq(CpuRegister dst, CpuRegister src) {
2290 void X86_64Assembler::popcntq(CpuRegister dst, const Address& src) {
2335 movsd(dst, Address(CpuRegister(RSP), 0));
2336 addq(CpuRegister(RSP), Immediate(2 * sizeof(intptr_t)));
2415 } else if (operand.IsRegister(CpuRegister(RAX))) {
2463 CpuRegister reg,
2485 CpuRegister operand,
2486 CpuRegister shifter) {
2522 void X86_64Assembler::EmitOptionalRex32(CpuRegister reg) {
2526 void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, CpuRegister src) {
2534 void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, XmmRegister src) {
2538 void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, CpuRegister src) {
2549 void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, const Operand& operand) {
2573 void X86_64Assembler::EmitRex64(CpuRegister reg) {
2583 void X86_64Assembler::EmitRex64(CpuRegister dst, CpuRegister src) {
2587 void X86_64Assembler::EmitRex64(XmmRegister dst, CpuRegister src) {
2591 void X86_64Assembler::EmitRex64(CpuRegister dst, XmmRegister src) {
2595 void X86_64Assembler::EmitRex64(CpuRegister dst, const Operand& operand) {
2611 void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src) {
2617 void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) {
2661 subq(CpuRegister(RSP), Immediate(rest_of_frame));
2670 movsd(Address(CpuRegister(RSP), offset), spill.AsXmmRegister());
2677 movq(Address(CpuRegister(RSP), 0), method_reg.AsX86_64().AsCpuRegister());
2683 movq(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()),
2687 movl(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsCpuRegister());
2691 movsd(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
2694 movss(Address(CpuRegister(RSP), frame_size + spill.getSpillOffset()), spill.AsX86_64().AsXmmRegister());
2711 movsd(spill.AsXmmRegister(), Address(CpuRegister(RSP), offset));
2718 addq(CpuRegister(RSP), Immediate(adjust));
2736 addq(CpuRegister(RSP), Immediate(-static_cast<int64_t>(adjust)));
2742 addq(CpuRegister(RSP), Immediate(adjust));
2753 movl(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
2756 movq(Address(CpuRegister(RSP), offs), src.AsCpuRegister());
2760 movq(Address(CpuRegister(RSP), offs), src.AsRegisterPairLow());
2761 movq(Address(CpuRegister(RSP), FrameOffset(offs.Int32Value()+4)),
2765 fstps(Address(CpuRegister(RSP), offs));
2767 fstpl(Address(CpuRegister(RSP), offs));
2772 movss(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
2774 movsd(Address(CpuRegister(RSP), offs), src.AsXmmRegister());
2782 movl(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
2788 movq(Address(CpuRegister(RSP), dest), src.AsCpuRegister());
2793 movl(Address(CpuRegister(RSP), dest), Immediate(imm)); // TODO(64) movq?
2806 leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), fr_offs));
2811 gs()->movq(Address::Absolute(thr_offs, true), CpuRegister(RSP));
2826 movl(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
2829 movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
2833 movq(dest.AsRegisterPairLow(), Address(CpuRegister(RSP), src));
2834 movq(dest.AsRegisterPairHigh(), Address(CpuRegister(RSP), FrameOffset(src.Int32Value()+4)));
2837 flds(Address(CpuRegister(RSP), src));
2839 fldl(Address(CpuRegister(RSP), src));
2844 movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
2846 movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), src));
2880 movq(dest.AsCpuRegister(), Address(CpuRegister(RSP), src));
2936 subl(CpuRegister(RSP), Immediate(16));
2939 fstps(Address(CpuRegister(RSP), 0));
2940 movss(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
2943 fstpl(Address(CpuRegister(RSP), 0));
2944 movsd(dest.AsXmmRegister(), Address(CpuRegister(RSP), 0));
2946 addq(CpuRegister(RSP), Immediate(16));
2957 movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), src));
2958 movl(Address(CpuRegister(RSP), dest), scratch.AsCpuRegister());
3002 pushq(Address(CpuRegister(RSP), src));
3008 CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
3010 movq(scratch, Address(CpuRegister(RSP), src_base));
3012 movq(Address(CpuRegister(RSP), dest), scratch);
3026 CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
3029 movq(scratch, Address(CpuRegister(RSP), src));
3047 movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3059 leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3062 leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3074 movl(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3077 leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3080 leaq(scratch.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
3118 CpuRegister scratch = mscratch.AsX86_64().AsCpuRegister();
3119 movq(scratch, Address(CpuRegister(RSP), base));
3134 movq(Address(CpuRegister(RSP), offset), scratch.AsCpuRegister());
3162 __ gs()->movq(CpuRegister(RDI), Address::Absolute(Thread::ExceptionOffset<8>(), true));
