Lines Matching refs:CpuRegister
97 bool IsRegister(CpuRegister reg) const {
111 void SetModRM(uint8_t mod_in, CpuRegister rm_in) {
120 void SetSIB(ScaleFactor scale_in, CpuRegister index_in, CpuRegister base_in) {
156 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); }
171 Address(CpuRegister base_in, int32_t disp) {
175 Address(CpuRegister base_in, Offset disp) {
179 Address(CpuRegister base_in, FrameOffset disp) {
181 Init(CpuRegister(RSP), disp.Int32Value());
184 Address(CpuRegister base_in, MemberOffset disp) {
188 void Init(CpuRegister base_in, int32_t disp) {
192 SetSIB(TIMES_1, CpuRegister(RSP), base_in);
197 SetSIB(TIMES_1, CpuRegister(RSP), base_in);
203 SetSIB(TIMES_1, CpuRegister(RSP), base_in);
210 Address(CpuRegister index_in, ScaleFactor scale_in, int32_t disp) {
212 SetModRM(0, CpuRegister(RSP));
213 SetSIB(scale_in, index_in, CpuRegister(RBP));
217 Address(CpuRegister base_in, CpuRegister index_in, ScaleFactor scale_in, int32_t disp) {
220 SetModRM(0, CpuRegister(RSP));
223 SetModRM(1, CpuRegister(RSP));
227 SetModRM(2, CpuRegister(RSP));
237 result.SetModRM(0, CpuRegister(RSP));
238 result.SetSIB(TIMES_1, CpuRegister(RSP), CpuRegister(RBP));
243 result.SetModRM(0, CpuRegister(RBP));
254 result.SetModRM(0, CpuRegister(RBP));
343 void call(CpuRegister reg);
347 void pushq(CpuRegister reg);
351 void popq(CpuRegister reg);
354 void movq(CpuRegister dst, const Immediate& src);
355 void movl(CpuRegister dst, const Immediate& src);
356 void movq(CpuRegister dst, CpuRegister src);
357 void movl(CpuRegister dst, CpuRegister src);
359 void movntl(const Address& dst, CpuRegister src);
360 void movntq(const Address& dst, CpuRegister src);
362 void movq(CpuRegister dst, const Address& src);
363 void movl(CpuRegister dst, const Address& src);
364 void movq(const Address& dst, CpuRegister src);
366 void movl(const Address& dst, CpuRegister src);
369 void cmov(Condition c, CpuRegister dst, CpuRegister src); // This is the 64b version.
370 void cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit);
371 void cmov(Condition c, CpuRegister dst, const Address& src, bool is64bit);
373 void movzxb(CpuRegister dst, CpuRegister src);
374 void movzxb(CpuRegister dst, const Address& src);
375 void movsxb(CpuRegister dst, CpuRegister src);
376 void movsxb(CpuRegister dst, const Address& src);
377 void movb(CpuRegister dst, const Address& src);
378 void movb(const Address& dst, CpuRegister src);
381 void movzxw(CpuRegister dst, CpuRegister src);
382 void movzxw(CpuRegister dst, const Address& src);
383 void movsxw(CpuRegister dst, CpuRegister src);
384 void movsxw(CpuRegister dst, const Address& src);
385 void movw(CpuRegister dst, const Address& src);
386 void movw(const Address& dst, CpuRegister src);
389 void leaq(CpuRegister dst, const Address& src);
390 void leal(CpuRegister dst, const Address& src);
398 void movsxd(CpuRegister dst, CpuRegister src);
399 void movsxd(CpuRegister dst, const Address& src);
401 void movd(XmmRegister dst, CpuRegister src); // Note: this is the r64 version, formally movq.
402 void movd(CpuRegister dst, XmmRegister src); // Note: this is the r64 version, formally movq.
403 void movd(XmmRegister dst, CpuRegister src, bool is64bit);
404 void movd(CpuRegister dst, XmmRegister src, bool is64bit);
428 void cvtsi2ss(XmmRegister dst, CpuRegister src); // Note: this is the r/m32 version.
429 void cvtsi2ss(XmmRegister dst, CpuRegister src, bool is64bit);
431 void cvtsi2sd(XmmRegister dst, CpuRegister src); // Note: this is the r/m32 version.
432 void cvtsi2sd(XmmRegister dst, CpuRegister src, bool is64bit);
435 void cvtss2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
439 void cvtsd2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
443 void cvttss2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
444 void cvttss2si(CpuRegister dst, XmmRegister src, bool is64bit);
445 void cvttsd2si(CpuRegister dst, XmmRegister src); // Note: this is the r32 version.
446 void cvttsd2si(CpuRegister dst, XmmRegister src, bool is64bit);
505 void xchgl(CpuRegister dst, CpuRegister src);
506 void xchgq(CpuRegister dst, CpuRegister src);
507 void xchgl(CpuRegister reg, const Address& address);
511 void cmpl(CpuRegister reg, const Immediate& imm);
512 void cmpl(CpuRegister reg0, CpuRegister reg1);
513 void cmpl(CpuRegister reg, const Address& address);
514 void cmpl(const Address& address, CpuRegister reg);
517 void cmpq(CpuRegister reg0, CpuRegister reg1);
518 void cmpq(CpuRegister reg0, const Immediate& imm);
519 void cmpq(CpuRegister reg0, const Address& address);
522 void testl(CpuRegister reg1, CpuRegister reg2);
523 void testl(CpuRegister reg, const Address& address);
524 void testl(CpuRegister reg, const Immediate& imm);
526 void testq(CpuRegister reg1, CpuRegister reg2);
527 void testq(CpuRegister reg, const Address& address);
529 void andl(CpuRegister dst, const Immediate& imm);
530 void andl(CpuRegister dst, CpuRegister src);
531 void andl(CpuRegister reg, const Address& address);
532 void andq(CpuRegister dst, const Immediate& imm);
533 void andq(CpuRegister dst, CpuRegister src);
534 void andq(CpuRegister reg, const Address& address);
536 void orl(CpuRegister dst, const Immediate& imm);
537 void orl(CpuRegister dst, CpuRegister src);
538 void orl(CpuRegister reg, const Address& address);
539 void orq(CpuRegister dst, CpuRegister src);
540 void orq(CpuRegister dst, const Immediate& imm);
541 void orq(CpuRegister reg, const Address& address);
543 void xorl(CpuRegister dst, CpuRegister src);
544 void xorl(CpuRegister dst, const Immediate& imm);
545 void xorl(CpuRegister reg, const Address& address);
546 void xorq(CpuRegister dst, const Immediate& imm);
547 void xorq(CpuRegister dst, CpuRegister src);
548 void xorq(CpuRegister reg, const Address& address);
550 void addl(CpuRegister dst, CpuRegister src);
551 void addl(CpuRegister reg, const Immediate& imm);
552 void addl(CpuRegister reg, const Address& address);
553 void addl(const Address& address, CpuRegister reg);
556 void addq(CpuRegister reg, const Immediate& imm);
557 void addq(CpuRegister dst, CpuRegister src);
558 void addq(CpuRegister dst, const Address& address);
560 void subl(CpuRegister dst, CpuRegister src);
561 void subl(CpuRegister reg, const Immediate& imm);
562 void subl(CpuRegister reg, const Address& address);
564 void subq(CpuRegister reg, const Immediate& imm);
565 void subq(CpuRegister dst, CpuRegister src);
566 void subq(CpuRegister dst, const Address& address);
571 void idivl(CpuRegister reg);
572 void idivq(CpuRegister reg);
574 void imull(CpuRegister dst, CpuRegister src);
575 void imull(CpuRegister reg, const Immediate& imm);
576 void imull(CpuRegister dst, CpuRegister src, const Immediate& imm);
577 void imull(CpuRegister reg, const Address& address);
579 void imulq(CpuRegister src);
580 void imulq(CpuRegister dst, CpuRegister src);
581 void imulq(CpuRegister reg, const Immediate& imm);
582 void imulq(CpuRegister reg, const Address& address);
583 void imulq(CpuRegister dst, CpuRegister reg, const Immediate& imm);
585 void imull(CpuRegister reg);
588 void mull(CpuRegister reg);
591 void shll(CpuRegister reg, const Immediate& imm);
592 void shll(CpuRegister operand, CpuRegister shifter);
593 void shrl(CpuRegister reg, const Immediate& imm);
594 void shrl(CpuRegister operand, CpuRegister shifter);
595 void sarl(CpuRegister reg, const Immediate& imm);
596 void sarl(CpuRegister operand, CpuRegister shifter);
598 void shlq(CpuRegister reg, const Immediate& imm);
599 void shlq(CpuRegister operand, CpuRegister shifter);
600 void shrq(CpuRegister reg, const Immediate& imm);
601 void shrq(CpuRegister operand, CpuRegister shifter);
602 void sarq(CpuRegister reg, const Immediate& imm);
603 void sarq(CpuRegister operand, CpuRegister shifter);
605 void negl(CpuRegister reg);
606 void negq(CpuRegister reg);
608 void notl(CpuRegister reg);
609 void notq(CpuRegister reg);
625 void jmp(CpuRegister reg);
631 void cmpxchgl(const Address& address, CpuRegister reg);
632 void cmpxchgq(const Address& address, CpuRegister reg);
638 void setcc(Condition condition, CpuRegister dst);
640 void bswapl(CpuRegister dst);
641 void bswapq(CpuRegister dst);
643 void bsfl(CpuRegister dst, CpuRegister src);
644 void bsfl(CpuRegister dst, const Address& src);
645 void bsfq(CpuRegister dst, CpuRegister src);
646 void bsfq(CpuRegister dst, const Address& src);
648 void bsrl(CpuRegister dst, CpuRegister src);
649 void bsrl(CpuRegister dst, const Address& src);
650 void bsrq(CpuRegister dst, CpuRegister src);
651 void bsrq(CpuRegister dst, const Address& src);
653 void popcntl(CpuRegister dst, CpuRegister src);
654 void popcntl(CpuRegister dst, const Address& src);
655 void popcntq(CpuRegister dst, CpuRegister src);
656 void popcntq(CpuRegister dst, const Address& src);
658 void rorl(CpuRegister reg, const Immediate& imm);
659 void rorl(CpuRegister operand, CpuRegister shifter);
660 void roll(CpuRegister reg, const Immediate& imm);
661 void roll(CpuRegister operand, CpuRegister shifter);
663 void rorq(CpuRegister reg, const Immediate& imm);
664 void rorq(CpuRegister operand, CpuRegister shifter);
665 void rolq(CpuRegister reg, const Immediate& imm);
666 void rolq(CpuRegister operand, CpuRegister shifter);
678 void AddImmediate(CpuRegister reg, const Immediate& imm);
682 void LockCmpxchgl(const Address& address, CpuRegister reg) {
686 void LockCmpxchgq(const Address& address, CpuRegister reg) {
857 void PoisonHeapReference(CpuRegister reg) { negl(reg); }
859 void UnpoisonHeapReference(CpuRegister reg) { negl(reg); }
861 void MaybeUnpoisonHeapReference(CpuRegister reg) {
883 void EmitGenericShift(bool wide, int rm, CpuRegister reg, const Immediate& imm);
884 void EmitGenericShift(bool wide, int rm, CpuRegister operand, CpuRegister shifter);
890 void EmitOptionalRex32(CpuRegister reg);
891 void EmitOptionalRex32(CpuRegister dst, CpuRegister src);
893 void EmitOptionalRex32(CpuRegister dst, XmmRegister src);
894 void EmitOptionalRex32(XmmRegister dst, CpuRegister src);
896 void EmitOptionalRex32(CpuRegister dst, const Operand& operand);
901 void EmitRex64(CpuRegister reg);
903 void EmitRex64(CpuRegister dst, CpuRegister src);
904 void EmitRex64(CpuRegister dst, const Operand& operand);
906 void EmitRex64(XmmRegister dst, CpuRegister src);
907 void EmitRex64(CpuRegister dst, XmmRegister src);
910 void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, CpuRegister src);
911 void EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand);
