Lines Matching refs:Rn
315 ArmRegister rn(instruction, 16);
316 if (rn.r == 0xf) {
322 args << "[" << rn << ", #" << offset << "]";
324 args << "[" << rn << ", #" << offset << "]!";
326 args << "[" << rn << "], #" << offset;
330 if (rn.r == 9) {
516 // |111|01|00|op|0|WL| Rn | |
525 ArmRegister Rn(instr, 16);
530 args << Rn << (W == 0 ? "" : "!") << ", ";
532 if (Rn.r != 13) {
534 args << Rn << (W == 0 ? "" : "!") << ", ";
541 if (Rn.r != 13) {
543 args << Rn << (W == 0 ? "" : "!") << ", ";
549 args << Rn << (W == 0 ? "" : "!") << ", ";
558 ArmRegister Rn(instr, 16);
572 args << Rt << "," << Rd << ", [" << Rn;
587 args << Rd << ", " << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
588 if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 ||
589 Rd.r == Rn.r || Rd.r == Rt.r) {
600 args << Rd << ", " << Rt << ", [" << Rn << "]";
601 if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 ||
602 Rd.r == Rn.r || Rd.r == Rt.r || (instr & 0xf00) != 0xf00) {
610 args << Rd << ", " << Rt << ", " << Rt2 << ", [" << Rn << "]";
612 Rt2.r == 13 || Rt2.r == 15 || Rn.r == 15 ||
613 Rd.r == Rn.r || Rd.r == Rt.r || Rd.r == Rt2.r) {
623 args << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]";
624 if (Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || (instr & 0xf00) != 0xf00) {
640 args << Rt << ", [" << Rn << "]";
641 if (Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || (instr & 0xf0f) != 0xf0f) {
647 args << Rt << ", " << Rd /* Rt2 */ << ", [" << Rn << "]";
649 Rn.r == 15 || (instr & 0x00f) != 0x00f) {
667 args << Rt << "," << Rd << ", [" << Rn;
689 // |111|0101| op3|S| Rn |imm3| Rd |i2|ty| Rm |
697 ArmRegister Rn(instr, 16);
714 if (Rn.r != 0xF) {
722 if (Rn.r != 0xF) {
779 if (Rn.r != 0xF) {
780 args << Rn << ", ";
813 // |111| |11| op3 | Rn | |copr| |op4| |
827 // |1110|110|PUDWL| Rn | Vd |101|S| imm8 |
836 ArmRegister Rn(instr, 16);
841 args << d << ", [" << Rn << ", #" << ((U == 1) ? "" : "-")
843 if (Rn.r == 15 && U == 1) {
846 } else if (Rn.r == 13 && W == 1 && U == L) { // VPUSH/VPOP
851 args << Rn << ((W == 1) ? "!" : "") << ", "
1076 // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii|
1081 ArmRegister Rn(instr, 16);
1086 if (Rn.r == 0xF && (op3 == 0x2 || op3 == 0x3)) {
1111 args << Rn << ", #" << ThumbExpand(imm32);
1129 args << Rd << ", " << Rn << ", #" << ThumbExpand(imm32);
1139 // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx|
1143 // ADD/SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii
1145 ArmRegister Rn(instr, 16);
1150 if (Rn.r != 0xF) {
1152 args << Rd << ", " << Rn << ", #" << imm12;
1166 uint32_t Rn = (instr >> 16) & 0xF;
1167 uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8;
1173 // BFI Rd, Rn, #lsb, #width - 111 10 0 11 011 0 nnnn 0 iii dddd ii 0 iiiii
1174 // SBFX Rd, Rn, #lsb, #width - 111 10 0 11 010 0 nnnn 0 iii dddd ii 0 iiiii
1175 // UBFX Rd, Rn, #lsb, #width - 111 10 0 11 110 0 nnnn 0 iii dddd ii 0 iiiii
1177 ArmRegister Rn(instr, 16);
1184 if (Rn.r != 0xF) {
1186 args << Rd << ", " << Rn << ", #" << lsb << ", #" << width;
1193 args << Rd << ", " << Rn << ", #" << lsb << ", #" << width;
1194 if (Rd.r == 13 || Rd.r == 15 || Rn.r == 13 || Rn.r == 15 ||
1347 // LDR{S}B imm12: 11111|00s1001| Rn | Rt |imm12 (0x09)
1348 // LDR{S}B imm8: 11111|00s0001| Rn | Rt |1PUW|imm8 (0x01)
1349 // LDR{S}BT imm8: 11111|00s0001| Rn | Rt |1110|imm8 (0x01)
1351 // LDR{S}B reg: 11111|00s0001| Rn | Rt |000000|imm2| Rm (0x01)
1352 // LDR{S}H imm12: 11111|00s1011| Rn | Rt |imm12 (0x0B)
1353 // LDR{S}H imm8: 11111|00s0011| Rn | Rt |1PUW|imm8 (0x03)
1354 // LDR{S}HT imm8: 11111|00s0011| Rn | Rt |1110|imm8 (0x03)
1356 // LDR{S}H reg: 11111|00s0011| Rn | Rt |000000|imm2| Rm (0x03)
1357 // LDR imm12: 11111|0001101| Rn | Rt |imm12 (0x0D)
1358 // LDR imm8: 11111|0000101| Rn | Rt |1PUW|imm8 (0x05)
1359 // LDRT imm8: 11111|0000101| Rn | Rt |1110|imm8 (0x05)
1361 // LDR reg: 11111|0000101| Rn | Rt |000000|imm2| Rm (0x05)
1364 // PLD{W} imm12: 11111|00010W1| Rn |1111|imm12 (0x09/0x0B)
1365 // PLD{W} imm8: 11111|00000W1| Rn |1111|1100|imm8 (0x01/0x03); -imm8
1367 // PLD{W} reg: 11111|00000W1| Rn |1111|000000|imm2| Rm (0x01/0x03)
1368 // PLI imm12: 11111|0011001| Rn |1111|imm12 (0x19)
1369 // PLI imm8: 11111|0010001| Rn |1111|1100|imm8 (0x11); -imm8
1371 // PLI reg: 11111|0010001| Rn |1111|000000|imm2| Rm (0x01/0x03)
1377 ArmRegister Rn(instr, 16);
1389 } else if (Rn.r == PC || U != 0u) {
1391 args << "[" << Rn << ", #" << (U != 0u ? "" : "-") << imm12 << "]";
1392 if (Rn.r == PC && is_half) {
1398 args << "[" << Rn << ", " << Rm << "]";
1401 args << "[" << Rn << ", #-" << imm8 << "]";
1411 if (Rn.r == PC && !is_load) {
1414 } else if (Rn.r == PC || U != 0u) {
1415 // Load/store with imm12 (load literal if Rn.r == PC; there's no store literal).
1417 args << Rt << ", [" << Rn << ", #" << (U != 0u ? "" : "-") << imm12 << "]";
1418 if (Rn.r == TR && is_load) {
1421 } else if (Rn.r == PC) {
1435 args << Rt << ", [" << Rn << ", " << Rm << "]";
1437 } else if (is_word && Rn.r == SP && imm8 == 4 && op4 == (is_load ? 0xB : 0xD)) {
1439 args << Rn;
1440 unpred = unpred || (Rn.r == SP);
1452 args << Rt << ", [" << Rn << (post_index ? "]" : "") << ", #" << (U != 0 ? "" : "-")
1454 unpred = (W != 0 && Rn.r == Rt.r);
1508 ArmRegister Rn(instr, 16);
1511 args << Rd << ", " << Rn << ", " << Rm;
1518 ArmRegister Rn(instr, 16);
1526 args << Rd << ", " << Rn << ", " << Rm;
1529 args << Rd << ", " << Rn << ", " << Rm << ", " << Ra;
1533 args << Rd << ", " << Rn << ", " << Rm << ", " << Ra;
1548 ArmRegister Rn(instr, 16);
1556 args << RdLo << ", " << RdHi << ", " << Rn << ", " << Rm;
1560 args << Rd << ", " << Rn << ", " << Rm;
1564 args << RdLo << ", " << RdHi << ", " << Rn << ", " << Rm;
1568 args << Rd << ", " << Rn << ", " << Rm;
1634 ThumbRegister Rn(instr, 3);
1645 args << Rd << ", " << Rn;
1659 // CMP Rn, #imm8 - 00101 nnn iiiiiiii
1660 // ADDS Rn, #imm8 - 00110 nnn iiiiiiii
1661 // SUBS Rn, #imm8 - 00111 nnn iiiiiiii
1662 ThumbRegister Rn(instr, 8);
1670 args << Rn << ", #" << imm8;
1713 uint16_t Rn = instr & 7;
1714 ArmRegister N_Rn((N << 3) | Rn);
1746 ThumbRegister Rn(instr, 3);
1758 args << Rt << ", [" << Rn << ", " << Rm << "]";
1768 ThumbRegister Rn(instr, 3);
1784 args << Rt << ", [" << Rn << ", #" << imm5 << "]";
1822 ThumbRegister Rn(instr, 0);
1825 args << Rn << ", ";
1906 // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt
1907 // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt
1909 ThumbRegister Rn(instr, 3);
1912 args << Rt << ", [" << Rn << ", #" << (imm5 << 2) << "]";
